Open64 (mfef90, whirl2f, and IR tools)
TAG: version-openad; SVN changeset: 916
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00001 /* 00002 00003 Copyright (C) 2000, 2001 Silicon Graphics, Inc. All Rights Reserved. 00004 00005 This program is free software; you can redistribute it and/or modify it 00006 under the terms of version 2 of the GNU General Public License as 00007 published by the Free Software Foundation. 00008 00009 This program is distributed in the hope that it would be useful, but 00010 WITHOUT ANY WARRANTY; without even the implied warranty of 00011 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 00012 00013 Further, this software is distributed without any warranty that it is 00014 free of the rightful claim of any third person regarding infringement 00015 or the like. Any license provided herein, whether implied or 00016 otherwise, applies only to this software file. Patent licenses, if 00017 any, provided herein do not apply to combinations of this program with 00018 other software, or any other product whatsoever. 00019 00020 You should have received a copy of the GNU General Public License along 00021 with this program; if not, write the Free Software Foundation, Inc., 59 00022 Temple Place - Suite 330, Boston MA 02111-1307, USA. 00023 00024 Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pky, 00025 Mountain View, CA 94043, or: 00026 00027 http://www.sgi.com 00028 00029 For further information regarding this notice, see: 00030 00031 http://oss.sgi.com/projects/GenInfo/NoticeExplan 00032 00033 */ 00034 00035 00036 /* ==================================================================== 00037 * ==================================================================== 00038 * 00039 * 00040 * 00041 * Description: 00042 * 00043 * Configuration specific to the target machine/system. 00044 * 00045 * NOTE: There is an approximate distinction between -TARG option 00046 * group flags and their configuration (in config_targ2.c), and more 00047 * generic target configuration (in this file). Note that the related 00048 * header file config_targ.h is included in config.h, and hence in most 00049 * source files, whereas config_targ2.h is only included directly, so 00050 * putting new -TARG option-related variables in config_targ2.c is to 00051 * be preferred to putting them here. 00052 * 00053 * ==================================================================== 00054 * ==================================================================== 00055 */ 00056 00057 #include "x_string.h" // for strcasecmp() 00058 00059 #include "defs.h" 00060 #include "config.h" 00061 #include "config_asm.h" 00062 #include "config_debug.h" 00063 #include "config_targ2.h" 00064 #include "config_opt.h" 00065 #include "erglob.h" 00066 #include "tracing.h" 00067 #include "mtypes.h" 00068 #include "stab.h" 00069 #include "targ_sim.h" 00070 00071 #if defined(FRONT_END_C) || defined(FRONT_END_CPLUSPLUS) 00072 typedef unsigned char an_integer_kind; 00073 #include "c_int_model.h" 00074 #endif 00075 00076 00077 /* Architecture specific definitions */ 00078 BOOL ARCH_generate_nor = FALSE; // Generate the NOR opcode 00079 BOOL ARCH_mask_shift_counts = FALSE; // shift counts are masked by the hardware (vs. truncated) 00080 00081 /* Target selection */ 00082 TARGET_ABI Target_ABI = ABI_UNDEF; 00083 TARGET_PROCESSOR Target = TARGET_UNDEF; /* -Tc */ 00084 TARGET_ISA Target_ISA = TARGET_ISA_UNDEF; /* -Tc.Ic */ 00085 00086 /* We need to know the machine type of the integer and floating point 00087 * registers for purposes of subprogram save/restore: 00088 */ 00089 CLASS_INDEX Spill_Int_Mtype = 0; 00090 CLASS_INDEX Spill_Float_Mtype = 0; 00091 00092 /* The maximum integer machine type corresponding directly to the 00093 * machine registers, and the default integer machine type: 00094 */ 00095 CLASS_INDEX Max_Int_Mtype = 0; 00096 CLASS_INDEX Max_Uint_Mtype = 0; 00097 CLASS_INDEX Def_Int_Mtype = 0; 00098 CLASS_INDEX Def_Uint_Mtype = 0; 00099 00100 /* On MIPS III targets, should we use 32-bit pointers? */ 00101 BOOL Use_32_Bit_Pointers = FALSE; 00102 00103 /* For various targets, what are the characteristics of pointers */ 00104 INT Pointer_Size; 00105 CLASS_INDEX Pointer_Mtype; 00106 CLASS_INDEX Pointer_Mtype2; 00107 00108 /* What are pointers and booleans aliased to in WHIRL */ 00109 TYPE_ID Pointer_type; 00110 TYPE_ID Pointer_type2; 00111 TYPE_ID Boolean_type; 00112 TYPE_ID Boolean_type2; 00113 TYPE_ID Integer_type; 00114 00115 /* For various targets, what is the comparison result type? */ 00116 INT Comparison_Result_Size; /* in bytes */ 00117 CLASS_INDEX Comparison_Result_Mtype; 00118 00119 /* The assembler directive for emitting an address depends on the target 00120 * pointer size. The following is declared in config_asm.h: 00121 */ 00122 char *AS_ADDRESS; 00123 char *AS_ADDRESS_UNALIGNED; 00124 00125 /* Is the "char" type signed? */ 00126 BOOL Char_Type_Is_Signed = FALSE; 00127 00128 /* Various categories which are static, for now: */ 00129 static BOOL Target_int64; /* 64-bit integer registers? */ 00130 00131 /* Miscellaneous exception control */ 00132 #define FPX_DEF EXC_ALL /* Default enables */ 00133 INT16 FP_Exception_Enable_Max = FPX_DEF;/* Max FP trap enables */ 00134 INT16 FP_Exception_Enable_Min = 0; /* Min FP trap enables */ 00135 00136 INT32 Align_Instructions = 0; /* 0 means hasn't been set */ 00137 BOOL Avoid_TFP_blikely_bug = FALSE; 00138 BOOL Avoid_TFP_blikely_bug_overridden = FALSE; 00139 00140 /***** IEEE 754 options *****/ 00141 BOOL Force_IEEE_Comparisons = TRUE; /* IEEE NaN comparisons? */ 00142 00143 /***** INTERNAL group options *****/ 00144 00145 BOOL WHIRL_Return_Val_On = TRUE; 00146 BOOL WHIRL_Mldid_Mstid_On = TRUE; 00147 BOOL WHIRL_Return_Info_On = TRUE; 00148 00149 00150 /* ==================================================================== 00151 * 00152 * Target debugging options 00153 * 00154 * ==================================================================== 00155 */ 00156 00157 /* Symbolic Debug mode as specified on command line. (The mode can 00158 * change from PU to PU because, for example, we encounter a call to 00159 * the routine 'alloca()' -- we must restore the mode to the value as 00160 * it was specified on the command line, so we remember it.) 00161 */ 00162 INT16 Symbolic_Debug_Mode; 00163 INT16 Max_Symbolic_Debug_Mode; /* Maximum for any PU */ 00164 00165 00166 /* ==================================================================== 00167 * 00168 * Miscellaneous options 00169 * 00170 * ==================================================================== 00171 */ 00172 00173 /* Can 64-bit values be 4-byte aligned in memory? */ 00174 BOOL Allow_Word_Aligned_Doubles = FALSE; 00175 00176 /* Should we generate position-independent code by default? */ 00177 BOOL Generate_Position_Independent_Code = FALSE; 00178 00179 /* Split 64-bit integer ops into 32-bit ops, and simulate them? */ 00180 BOOL Split_64_Bit_Int_Ops = FALSE; 00181 00182 /* Split quad-precision ops into double-precision, and simulate them? */ 00183 BOOL Split_Quad_Ops = TRUE; 00184 00185 /* Should we simulate 32-bit subprogram interface by default? */ 00186 BOOL Simulate_32_Bit_Interface = FALSE; 00187 00188 /* Work around a TFP branch cache problem. */ 00189 BOOL No_Quad_Aligned_Branch = FALSE; 00190 00191 /* Does target provides only unsigned 64-bit instructions? */ 00192 BOOL Only_Unsigned_64_Bit_Ops = TRUE; 00193 00194 BOOL Has_GP_Groups = FALSE; 00195 00196 /* Does target have offsets in load and store instructions? 00197 * Note: CG should instead test: 00198 * ( TOP_Find_Operand_Use( OP_code(op), OU_offset ) >= 0 ) */ 00199 BOOL Use_Load_Store_Offset = FALSE; 00200 00201 #if defined (FRONT_END_C) || defined (FRONT_END_CPLUSPLUS) 00202 00203 PREG_NUM Map_Reg_To_Preg [] = { 00204 /* General registers. */ 00205 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007, 00206 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f, 00207 0x010, 0x011, 0x012, 0x013, 0x014, 0x015, 0x016, 0x017, 00208 0x018, 0x019, 0x01a, 0x01b, 0x01c, 0x01d, 0x01e, 0x01f, 00209 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 00210 0x028, 0x029, 0x02a, 0x02b, 0x02c, 0x02d, 0x02e, 0x02f, 00211 0x030, 0x031, 0x032, 0x033, 0x034, 0x035, 0x036, 0x037, 00212 0x038, 0x039, 0x03a, 0x03b, 0x03c, 0x03d, 0x03e, 0x03f, 00213 0x040, 0x041, 0x042, 0x043, 0x044, 0x045, 0x046, 0x047, 00214 0x048, 0x049, 0x04a, 0x04b, 0x04c, 0x04d, 0x04e, 0x04f, 00215 0x050, 0x051, 0x052, 0x053, 0x054, 0x055, 0x056, 0x057, 00216 0x058, 0x059, 0x05a, 0x05b, 0x05c, 0x05d, 0x05e, 0x05f, 00217 0x060, 0x061, 0x062, 0x063, 0x064, 0x065, 0x066, 0x067, 00218 0x068, 0x069, 0x06a, 0x06b, 0x06c, 0x06d, 0x06e, 0x06f, 00219 0x070, 0x071, 0x072, 0x073, 0x074, 0x075, 0x076, 0x077, 00220 0x078, 0x079, 0x07a, 0x07b, 0x07c, 0x07d, 0x07e, 0x07f, 00221 /* Floating-point registers. */ 00222 0x080, 0x081, 0x082, 0x083, 0x084, 0x085, 0x086, 0x087, 00223 0x088, 0x089, 0x08a, 0x08b, 0x08c, 0x08d, 0x08e, 0x08f, 00224 0x090, 0x091, 0x092, 0x093, 0x094, 0x095, 0x096, 0x097, 00225 0x098, 0x099, 0x09a, 0x09b, 0x09c, 0x09d, 0x09e, 0x09f, 00226 0x0a0, 0x0a1, 0x0a2, 0x0a3, 0x0a4, 0x0a5, 0x0a6, 0x0a7, 00227 0x0a8, 0x0a9, 0x0aa, 0x0ab, 0x0ac, 0x0ad, 0x0ae, 0x0af, 00228 0x0b0, 0x0b1, 0x0b2, 0x0b3, 0x0b4, 0x0b5, 0x0b6, 0x0b7, 00229 0x0b8, 0x0b9, 0x0ba, 0x0bb, 0x0bc, 0x0bd, 0x0be, 0x0bf, 00230 0x0c0, 0x0c1, 0x0c2, 0x0c3, 0x0c4, 0x0c5, 0x0c6, 0x0c7, 00231 0x0c8, 0x0c9, 0x0ca, 0x0cb, 0x0cc, 0x0cd, 0x0ce, 0x0cf, 00232 0x0d0, 0x0d1, 0x0d2, 0x0d3, 0x0d4, 0x0d5, 0x0d6, 0x0d7, 00233 0x0d8, 0x0d9, 0x0da, 0x0db, 0x0dc, 0x0dd, 0x0de, 0x0df, 00234 0x0e0, 0x0e1, 0x0e2, 0x0e3, 0x0e4, 0x0e5, 0x0e6, 0x0e7, 00235 0x0e8, 0x0e9, 0x0ea, 0x0eb, 0x0ec, 0x0ed, 0x0ee, 0x0ef, 00236 0x0f0, 0x0f1, 0x0f2, 0x0f3, 0x0f4, 0x0f5, 0x0f6, 0x0f7, 00237 0x0f8, 0x0f9, 0x0fa, 0x0fb, 0x0fc, 0x0fd, 0x0fe, 0x0ff, 00238 /* Predicate registers. */ 00239 -1, -1, -1, -1, -1, -1, -1, -1, 00240 -1, -1, -1, -1, -1, -1, -1, -1, 00241 -1, -1, -1, -1, -1, -1, -1, -1, 00242 -1, -1, -1, -1, -1, -1, -1, -1, 00243 -1, -1, -1, -1, -1, -1, -1, -1, 00244 -1, -1, -1, -1, -1, -1, -1, -1, 00245 -1, -1, -1, -1, -1, -1, -1, -1, 00246 -1, -1, -1, -1, -1, -1, -1, -1, 00247 /* Branch registers. */ 00248 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107, 00249 /* Outgoing registers. */ 00250 0x07f, 0x07e, 0x07d, 0x07c, 0x07b, 0x07a, 0x079, 0x078, 00251 /* FP */ 00252 -1 00253 }; 00254 00255 #endif /* defined (FRONT_END_C) || defined (FRONT_END_CPLUSPLUS) */ 00256 00257 00258 /* ==================================================================== 00259 * 00260 * Abi_Name / Isa_Name / Targ_Name 00261 * 00262 * Produce printable names for the target choices. 00263 * 00264 * ==================================================================== 00265 */ 00266 00267 static struct bnm { 00268 char name[16]; 00269 } bnb[4]; 00270 static INT16 bnb_used = 0; 00271 00272 #ifndef MONGOOSE_BE 00273 char * 00274 Abi_Name ( TARGET_ABI b) 00275 { 00276 char *r; 00277 00278 switch ( b ) { 00279 case ABI_I32: return "i32"; 00280 case ABI_I64: return "i64"; 00281 default: 00282 r = bnb[bnb_used].name; 00283 bnb_used = (bnb_used + 1) % 4; 00284 sprintf (r, "ABI_%d", b); 00285 return r; 00286 } 00287 } 00288 #endif /* MONGOOSE_BE */ 00289 00290 char * 00291 Isa_Name ( TARGET_ISA b) 00292 { 00293 char *r; 00294 00295 switch ( b ) { 00296 default: 00297 r = bnb[bnb_used].name; 00298 bnb_used = (bnb_used + 1) % 4; 00299 sprintf (r, "ISA_%d", b); 00300 return r; 00301 } 00302 } 00303 00304 char * 00305 Targ_Name ( TARGET_PROCESSOR b) 00306 { 00307 char *r; 00308 00309 switch ( b ) { 00310 case TARGET_ITANIUM: return "Itanium"; 00311 default: 00312 r = bnb[bnb_used].name; 00313 bnb_used = (bnb_used + 1) % 4; 00314 sprintf (r, "PROCESSOR_%d", b); 00315 return r; 00316 } 00317 } 00318 00319 /* ==================================================================== 00320 * 00321 * Preconfigure_Target 00322 * 00323 * Configuration of target-specific parameters, before flag processing. 00324 * 00325 * ==================================================================== 00326 */ 00327 00328 void 00329 Preconfigure_Target ( void ) 00330 { 00331 return; 00332 } 00333 00334 /* ==================================================================== 00335 * 00336 * Prepare_Target 00337 * 00338 * Given target specification choices, fill in defaulted pieces and 00339 * check for conflicting specifications. When this routine is done, 00340 * ABI, Target_ISA, Target, and Target_FPRs are all valid. We also 00341 * use the target information to set the descriptive variables 00342 * Target_int64, Target_Int_Model, and Use_32_Bit_Pointers. 00343 * 00344 * TODO: Pending final conversion of the driver, we may have incoming 00345 * information from either or both of -T... and -TARG:... options. We 00346 * effectively give precedence to the -TARG: specifications, and after 00347 * final conversion should remove the -T support. Note that we ignore 00348 * the pointer size and integer model specifications from -Tx,Pnn,Mm. 00349 * 00350 * ==================================================================== 00351 */ 00352 00353 static void 00354 Prepare_Target ( void ) 00355 { 00356 TARGET_ISA isa_default = TARGET_ISA_UNDEF; 00357 TARGET_PROCESSOR targ_default = TARGET_UNDEF; 00358 00359 /* First check the ABI: */ 00360 if ( ABI_Name != NULL ) { 00361 if ( strcmp ( ABI_Name, "i32" ) == 0 ) { 00362 Target_ABI = ABI_I32; 00363 isa_default = TARGET_ISA_I1; 00364 targ_default = TARGET_ITANIUM; 00365 } else if ( strcmp ( ABI_Name, "i64" ) == 0 ) { 00366 Target_ABI = ABI_I64; 00367 isa_default = TARGET_ISA_I1; 00368 targ_default = TARGET_ITANIUM; 00369 } else if (strcmp ( ABI_Name, "ia32" ) == 0) { 00370 //WEI: I hope this is correct... 00371 Target_ABI = ABI_I32; 00372 isa_default = TARGET_ISA_I1; 00373 targ_default = TARGET_ITANIUM; 00374 } else { 00375 ErrMsg ( EC_Inv_TARG, "abi", ABI_Name ); 00376 } 00377 } 00378 00379 /* Next check the ISA from -TARG:isa=xxx: */ 00380 if ( ISA_Name != NULL ) { 00381 TARGET_ISA isa; 00382 00383 if ( ux_strcasecmp ( ISA_Name, "intel1" ) == 0 ) { 00384 isa = TARGET_ISA_I1; 00385 targ_default = TARGET_ITANIUM; 00386 } else 00387 { 00388 ErrMsg ( EC_Inv_TARG, "isa", ISA_Name ); 00389 } 00390 00391 /* If there's an ISA from -Tn,Ix it must match: */ 00392 if ( Target_ISA != TARGET_ISA_UNDEF && Target_ISA != isa ) { 00393 ErrMsg ( EC_Incons_TARG, "isa", ISA_Name, 00394 "isa", Isa_Name(Target_ISA) ); 00395 } 00396 Target_ISA = isa; 00397 } 00398 00399 /* Now make sure ISA and ABI are consistent if both specified, 00400 * and if one is default the other: 00401 */ 00402 switch ( Target_ISA ) { 00403 case TARGET_ISA_UNDEF: 00404 Target_ISA = isa_default; 00405 break; 00406 } 00407 00408 /* Now check the target processor from -TARG:processor=xxx: */ 00409 if ( Processor_Name != NULL ) { 00410 TARGET_PROCESSOR targ; 00411 00412 if ( ux_strcasecmp ( Processor_Name, "itanium" ) == 0 ) { 00413 targ = TARGET_ITANIUM; 00414 } else { 00415 ErrMsg ( EC_Inv_TARG, "processor", Processor_Name ); 00416 targ = TARGET_UNDEF; 00417 } 00418 00419 /* If there's a processor spec from -Tn it must match: */ 00420 if ( Target != TARGET_UNDEF && Target != targ ) { 00421 ErrMsg ( EC_Incons_TARG, "processor", Processor_Name, 00422 "processor", Targ_Name(Target) ); 00423 } 00424 Target = targ; 00425 } 00426 00427 /* Now make sure ABI/ISA and Target are consistent if both specified, 00428 * and if one is default the other: 00429 */ 00430 switch ( Target ) { 00431 case TARGET_ITANIUM: 00432 Target_ABI = ABI_I64; 00433 Target_ISA = TARGET_ISA_I1; 00434 Target = TARGET_ITANIUM; 00435 break; 00436 case TARGET_UNDEF: 00437 Target = targ_default; 00438 if ( Target == TARGET_UNDEF ) { 00439 /* Default everything: */ 00440 Target_ABI = ABI_I64; 00441 Target_ISA = TARGET_ISA_I1; 00442 Target = TARGET_ITANIUM; 00443 } 00444 break; 00445 } 00446 00447 /* Now deal with FP register count: */ 00448 switch ( Target_FPRs ) { 00449 default: /* Invalid value */ 00450 ErrMsg ( EC_Inv_FPRs, Target_FPRs ); 00451 /* fall through */ 00452 case 0: /* Unspecified */ 00453 Target_FPRs = 128; 00454 break; 00455 case 16: /* Always OK, warning possible */ 00456 ErrMsg ( EC_FPR_16 ); 00457 break; 00458 case 32: 00459 ErrMsg ( EC_FPR_32 ); 00460 break; 00461 } 00462 00463 /* Set descriptive variables: */ 00464 Target_int64 = TRUE; 00465 Use_32_Bit_Pointers = (Target_ABI == ABI_I32); 00466 #if defined(FRONT_END_C) || defined(FRONT_END_CPLUSPLUS) 00467 Target_Int_Model = ( Target_ABI == ABI_I64 ) ? TARGET_INT_LP64 00468 : TARGET_INT_ILP32; 00469 Make_Int_Model_Consistent (); 00470 #endif 00471 } 00472 00473 /* ==================================================================== 00474 * 00475 * Configure_Target 00476 * 00477 * Configuration of target-specific parameters, after flag processing. 00478 * 00479 * ==================================================================== 00480 */ 00481 00482 void 00483 Configure_Target ( void ) 00484 { 00485 00486 #if defined(linux) 00487 Target_Byte_Sex = LITTLE_ENDIAN; 00488 #else 00489 Target_Byte_Sex = BIG_ENDIAN; 00490 #endif 00491 Same_Byte_Sex = ( Target_Byte_Sex == Host_Byte_Sex ); 00492 00493 Gen_PIC_Calls = FALSE; // ld handle's pic calls for IA-64 00494 GP_Is_Preserved = FALSE; 00495 00496 /* Set up the target processor and ISA: */ 00497 Prepare_Target (); 00498 00499 /* Unrolling defaults */ 00500 if (OPT_unroll_times > 0 && !OPT_unroll_times_overridden) 00501 OPT_unroll_times = 4; 00502 00503 /* Set up the target register set: */ 00504 switch ( Target_ISA ) { 00505 case TARGET_ITANIUM: 00506 Spill_Int_Mtype = MTYPE_I8; 00507 Spill_Float_Mtype = MTYPE_F16; 00508 Max_Int_Mtype = Def_Int_Mtype = MTYPE_I8; 00509 Max_Uint_Mtype = Def_Uint_Mtype = MTYPE_U8; 00510 Boolean_type = MTYPE_I4; 00511 Boolean_type2 = MTYPE_I4; 00512 Integer_type = MTYPE_I4; 00513 00514 Split_Quad_Ops = TRUE; 00515 Split_64_Bit_Int_Ops = FALSE; 00516 break; 00517 } 00518 00519 #if defined(FRONT_END_C) || defined(FRONT_END_CPLUSPLUS) 00520 #ifndef EDG_FORTRAN 00521 Make_Int_Model_Consistent(); 00522 #endif 00523 #endif 00524 00525 /* Initialize pointer information */ 00526 if ( Use_32_Bit_Pointers ) { 00527 //cout << "GOT HERE!!!!!" << endl; 00528 Pointer_Size = 4; 00529 Pointer_Mtype = WHIRL_Mtype_A_On ? MTYPE_A4 : MTYPE_U4; 00530 Pointer_type = Pointer_Mtype; 00531 Pointer_Mtype2 = MTYPE_U4; 00532 Pointer_type2 = MTYPE_U4; 00533 } else { 00534 Pointer_Size = 8; 00535 Pointer_Mtype = WHIRL_Mtype_A_On ? MTYPE_A8: MTYPE_U8; 00536 Pointer_type = Pointer_Mtype; 00537 Pointer_Mtype2 = MTYPE_U8; 00538 Pointer_type2 = MTYPE_U8; 00539 } 00540 00541 if ( Use_32_Bit_Pointers ) { 00542 AS_ADDRESS = AS_WORD; 00543 AS_ADDRESS_UNALIGNED = AS_WORD; 00544 } else { 00545 AS_ADDRESS = AS_DWORD; 00546 AS_ADDRESS_UNALIGNED = AS_DWORD_UNALIGNED; 00547 } 00548 00549 /* If the user has requested aggregate alignment without specifying 00550 * a threshhold, set it to the register size. Otherwise, make sure 00551 * it's a power of two. WARNING: The option group processing sets 00552 * it to -1 if no threshhold is given, and otherwise restricts it to 00553 * a reasonable range, so we don't worry about overflow or bad values. 00554 * Also, if the user has "turned down" alignment, don't try to 00555 * realign objects (pv 525474) 00556 */ 00557 if ( Aggregate_Alignment > 0 ) { 00558 INT32 i = 1; 00559 while ( i < Aggregate_Alignment ) i <<= 1; 00560 Aggregate_Alignment = i; 00561 00562 if (Aggregate_Alignment < (Target_int64 ? 8 : 4)) 00563 { 00564 Align_Object = FALSE; 00565 } 00566 } 00567 00568 #if defined(BACK_END) 00569 Init_Targ_Sim(); /* must be done before initialize_stack_frame */ 00570 #endif 00571 00572 #define IS_POW2(n) (((n) & ((n)-1))==0) 00573 FmtAssert (IS_POW2(Align_Instructions), 00574 ("-OPT:align_instructions=<n> must equal power of two")); 00575 00576 return; 00577 } 00578 00579 /* ==================================================================== 00580 * 00581 * IPA_Configure_Target 00582 * 00583 * IPA-specific configuration. Similar to Configure_Target but only set up 00584 * those variables that IPA cares. 00585 * 00586 * ==================================================================== 00587 */ 00588 void 00589 IPA_Configure_Target (void) 00590 { 00591 if (Target_ABI == ABI_I32) { 00592 Pointer_Size = 4; 00593 Pointer_Mtype = WHIRL_Mtype_A_On ? MTYPE_A4 : MTYPE_U4; 00594 Pointer_type = Pointer_Mtype; 00595 Pointer_Mtype2 = MTYPE_U4; 00596 Pointer_type2 = MTYPE_U4; 00597 } else { 00598 Pointer_Size = 8; 00599 Pointer_Mtype = WHIRL_Mtype_A_On ? MTYPE_A8 : MTYPE_U8; 00600 Pointer_type = Pointer_Mtype; 00601 Pointer_Mtype2 = MTYPE_U8; 00602 Pointer_type2 = MTYPE_U8; 00603 } 00604 00605 Integer_type = MTYPE_I4; 00606 Boolean_type = MTYPE_I4; 00607 Boolean_type2 = MTYPE_I4; 00608 00609 } /* IPA_Configure_Target */ 00610 00611 /* ==================================================================== 00612 * 00613 * Configure_Source_Target 00614 * 00615 * Reconfiguration of target-specific parameters for each source file. 00616 * 00617 * ==================================================================== 00618 */ 00619 00620 void 00621 Configure_Source_Target ( char * /* filename */ ) 00622 { 00623 char *option; 00624 00625 /* IA-64 doesn't have index loads. 00626 */ 00627 Indexed_Loads_Allowed = FALSE; 00628 00629 /* pv #297274 describes why we cannot put initialized data in .bss */ 00630 if ( Kernel_Code ) { 00631 Zeroinit_in_bss = FALSE; 00632 } 00633 00634 /* Miscellaneous exception control */ 00635 if ( FP_Excp_Max != NULL ) { 00636 FP_Exception_Enable_Max = 0; 00637 option = FP_Excp_Max; 00638 while ( *option ) { 00639 switch ( *option ) { 00640 case 'I': FP_Exception_Enable_Max |= FPX_I; break; 00641 case 'U': FP_Exception_Enable_Max |= FPX_U; break; 00642 case 'O': FP_Exception_Enable_Max |= FPX_O; break; 00643 case 'Z': FP_Exception_Enable_Max |= FPX_Z; break; 00644 case 'V': FP_Exception_Enable_Max |= FPX_V; break; 00645 } 00646 option++; 00647 } 00648 } 00649 if ( FP_Excp_Min != NULL ) { 00650 FP_Exception_Enable_Min = 0; 00651 option = FP_Excp_Min; 00652 while ( *option ) { 00653 switch ( *option ) { 00654 case 'I': FP_Exception_Enable_Min |= FPX_I; break; 00655 case 'U': FP_Exception_Enable_Min |= FPX_U; break; 00656 case 'O': FP_Exception_Enable_Min |= FPX_O; break; 00657 case 'Z': FP_Exception_Enable_Min |= FPX_Z; break; 00658 case 'V': FP_Exception_Enable_Min |= FPX_V; break; 00659 } 00660 option++; 00661 } 00662 } 00663 00664 if ( DEBUG_Trap_Uv ) 00665 FP_Exception_Enable_Min |= FPX_V; 00666 00667 // TMP: ignore cpic until we figure out what to do with it 00668 if (Gen_PIC_Call_Shared) 00669 Gen_PIC_Call_Shared = FALSE; 00670 00671 return; 00672 } 00673 00674 /* return FALSE if abi mismatch */ 00675 extern BOOL 00676 Set_Target_ABI (BOOL is_64bit, INT isa) 00677 { 00678 if (is_64bit) { 00679 switch (Target_ABI) { 00680 case ABI_UNDEF: 00681 Target_ABI = ABI_I64; 00682 break; 00683 case ABI_I64: 00684 break; 00685 default: 00686 return FALSE; 00687 } 00688 } else { /* 32 */ 00689 switch (Target_ABI) { 00690 case ABI_UNDEF: 00691 Target_ABI = ABI_I32; 00692 break; 00693 case ABI_I32: 00694 break; 00695 default: 00696 return FALSE; 00697 } 00698 } 00699 00700 if (Target_ISA == TARGET_ISA_UNDEF) { 00701 Target_ISA = TARGET_ISA_I1; 00702 } 00703 00704 return TRUE; 00705 }