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Open64 (mfef90, whirl2f, and IR tools)
TAG: version-openad; SVN changeset: 916
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Open64 (mfef90, whirl2f, and IR tools)
TAG: version-openad; SVN changeset: 916
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00001 /* 00002 00003 Copyright (C) 2000, 2001 Silicon Graphics, Inc. All Rights Reserved. 00004 00005 This program is free software; you can redistribute it and/or modify it 00006 under the terms of version 2 of the GNU General Public License as 00007 published by the Free Software Foundation. 00008 00009 This program is distributed in the hope that it would be useful, but 00010 WITHOUT ANY WARRANTY; without even the implied warranty of 00011 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 00012 00013 Further, this software is distributed without any warranty that it is 00014 free of the rightful claim of any third person regarding infringement 00015 or the like. Any license provided herein, whether implied or 00016 otherwise, applies only to this software file. Patent licenses, if 00017 any, provided herein do not apply to combinations of this program with 00018 other software, or any other product whatsoever. 00019 00020 You should have received a copy of the GNU General Public License along 00021 with this program; if not, write the Free Software Foundation, Inc., 59 00022 Temple Place - Suite 330, Boston MA 02111-1307, USA. 00023 00024 Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pky, 00025 Mountain View, CA 94043, or: 00026 00027 http://www.sgi.com 00028 00029 For further information regarding this notice, see: 00030 00031 http://oss.sgi.com/projects/GenInfo/NoticeExplan 00032 00033 */ 00034 00035 00036 // 00037 // Group TOPS with similar packing format together. 00039 // The instructions are listed by category. The different categories of 00040 // instructions are: 00041 // 00042 // 1. ALU 00043 // 2. Integer 00044 // 3. Memory 00045 // 4. Branch 00046 // 5. Float 00047 // 00048 // Within each Pack_Type instructions are listed in the order as shown 00049 // in the IA-64 instructions formats manual 00051 00052 #include <stddef.h> 00053 #include "topcode.h" 00054 #include "isa_pack_gen.h" 00055 00056 main() 00057 { 00058 ISA_PACK_TYPE a1, // Integer ALU -- Register-Register 00059 a2, // Shift Left and Add 00060 a3, // Integer ALU -- Immediate_8-Register 00061 a4, // Add Immediate_14 00062 a5, // Add Immediate_22 00063 a6, // Integer Compare -- Register-Register 00064 a7, // Integer Compare to Zero -- Register 00065 a8a, // Integer Compare -- Immediate-Register 00066 a8b, // Integer Compare -- Immediate-Register 00067 a9, // Multimedia ALU 00068 a10, // Multimedia Shift and Add 00069 a11, // Move General Register (pseudo) 00070 a12, // Move Immediate (pseudo) 00071 a13, // Integer Compare -- Register-Register (pseudo) 00072 a14, // Integer Compare -- Register-Register (pseudo) 00073 a15, // Integer Compare -- Register-Register (pseudo) 00074 a16, // Integer Compare -- Register-Register (pseudo) 00075 a17, // Integer Compare -- Immediate-Register (pseudo) 00076 a18, // Integer Compare -- Immediate-Register (pseudo) 00077 a19, // Integer Compare -- Immediate-Register (pseudo) 00078 a20, // Integer Compare -- Immediate-Register (pseudo) 00079 a21, // Integer Compare -- Immediate-Register (pseudo) 00080 a22, // Integer Compare to Zero -- Register (pseudo) 00081 a23; // Integer Compare to Zero -- Register (pseudo) 00082 00083 ISA_PACK_TYPE i1, // Multimedia Multiply and Shift 00084 i2, // Multimedia Multiply/Mix/Pack/Unpack 00085 i3, // Multimedia Mux1 00086 i4, // Multimedia Mux2 00087 i5, // Shift Right -- Variable 00088 i6, // Multimedia Shift Right -- Fixed 00089 i7, // Shift Left -- Variable 00090 i8, // Multimedia Shift Left -- Fixed 00091 i9, // Population Count 00092 i10, // Shift Right Pair 00093 i11, // Extract 00094 i12, // Zero and Deposit 00095 i13, // Zero and Deposit Immediate_8 00096 i14, // Deposit Immediate_1 00097 i15, // Deposit 00098 i16, // Test Bit 00099 i17, // Test NaT 00100 // i18, // Move Long Immediate_64 (NOTE: now X2) 00101 i19, // Break/Nop 00102 i20, // Integer Speculation Check 00103 i21, // Move to BR 00104 i22, // Move from BR 00105 i23, // Move to Predicates -- Register 00106 i24, // Move to Predicates -- Immediate_44 00107 i25, // Move from Predicates/IP 00108 i26, // Move to AR -- Register 00109 i27, // Move to AR -- Immediate_8 00110 i28, // Move from AR 00111 i29, // Sign/Zero Extend/Compute Zero Index 00112 i30, // Move to BR (pseudo) 00113 i31, // Test Bit (pseudo) 00114 i32, // Test NaT (pseudo) 00115 i33, // Shift Left Immediate (pseudo) 00116 i34; // Shift Right Immediate (pseudo) 00117 00118 ISA_PACK_TYPE m1a, // Integer Load 00119 m1b, // Integer Load 00120 m2a, // Integer Load -- Increment by Register 00121 m2b, // Integer Load -- Increment by Register 00122 m3a, // Integer Load -- Increment by Immediate 00123 m3b, // Integer Load -- Increment by Immediate 00124 m4a, // Integer Store 00125 m4b, // Integer Store 00126 m5a, // Integer Store -- Increment by Immediate 00127 m5b, // Integer Store -- Increment by Immediate 00128 m6a, // Floating-point Load 00129 m6b, // Floating-point Load 00130 m7a, // Floating-point Load -- Increment by Register 00131 m7b, // Floating-point Load -- Increment by Register 00132 m8a, // Floating-point Load -- Increment by Immediate 00133 m8b, // Floating-point Load -- Increment by Immediate 00134 m9, // Floating-point Store 00135 m10, // Floating-point Store -- Increment by Immediate 00136 m11, // Floating-point Load Pair 00137 m12, // Floating-point Load Pair -- Increment by Immediate 00138 m13, // Line Prefetch 00139 m14, // Line Prefetch -- Increment by Register 00140 m15, // Line Prefetch -- Increment by Immediate 00141 m16a, // Exchange/Compare and Exchange 00142 m16b, // Exchange/Compare and Exchange 00143 m17, // Fetch and Add -- Immediate 00144 m18, // Set FR 00145 m19, // Get FR 00146 m20, // Integer Speculation Check 00147 m21, // Floating-point Speculation Check 00148 m22, // Integer Advanced Load Check 00149 m23, // Floating-point Advanced Load Check 00150 m24, // Sync/Fence/Serialize/ALAT Control 00151 m25, // RSE Control 00152 m26, // Integer ALAT Entry Invalidate 00153 m27, // Floating-point ALAT Entry Invalidate 00154 m28, // Flush Cache/Purge Translation Cache Entry 00155 m29, // Move to AR -- Register 00156 m30, // Move to AR -- Immediate_8 00157 m31, // Move from AR 00158 m32, // Move to CR 00159 m33, // Move from CR 00160 m34, // Allocate Register Stack Frame 00161 m35, // Move to PSR 00162 m36, // Move from PSR 00163 m37, // Break/Nop 00164 m38, // Probe -- Register 00165 m39, // Probe -- Immediate_2 00166 m40, // Probe Fault 00167 m41, // Translation Cache Insert 00168 m42, // Move to Indirect Register/Translation Register Insert 00169 m43, // Move from Indirect Register 00170 m44, // Set/Reset User/System Mask 00171 m45, // Translation Purge 00172 m46, // Translation Access 00173 m47; // Allocate Register Stack Frame (pseudo) 00174 00175 ISA_PACK_TYPE b1, // IP-Relative Branch 00176 b2, // IP-Relative Counted Branch 00177 b3, // IP-Relative Call 00178 b4, // Indirect Branch 00179 b4a, // Indirect Branch 00180 b5, // Indirect Call 00181 b6, // IP-Relative Predict 00182 b7, // Indirect Predict 00183 b8, // Miscellaneous 00184 b9, // Break/Nop 00185 b10, // IP-Relative Unconditional Branch (pseudo) 00186 b11; // Indirect Unconditional Branch (pseudo) 00187 00188 ISA_PACK_TYPE f1, // Floating-point Multiply Add 00189 f2, // Fixed-point Multiply Add 00190 f3, // Parallel Floating-point Select 00191 f4, // Floating-point Compare 00192 f5, // Floating-point Class 00193 f6, // Floating-point Reciprocal Approximation 00194 f7, // Floating-point Reciprocal Square Root Approximation 00195 f8, // Minimum/Maximum and Parallel Compare 00196 f9, // Merge and Logical 00197 f10, // Convert Floating-point to Fixed-point 00198 f11, // Convert Fixed-point to Floating-point 00199 f12, // Floating-point Set Controls 00200 f13, // Floating-point Clear Flags 00201 f14, // Floating-point Check Flags 00202 f15, // Break/Nop 00203 f16, // Floating-point Absolute Value (pseudo) 00204 f17, // Floating-point Negate (pseudo) 00205 f18, // Fixed-point Multiply Add (pseudo) 00206 f19, // Fixed-point Multiply (pseudo) 00207 f20, // Convert Unsigned Integer to Floating-point (pseudo) 00208 f21, // Floating-point Add/Subtract (pseudo) 00209 f22, // Floating-point Multiply (pseudo) 00210 f23, // Floating-point Class (pseudo) 00211 f24, // Floating-point Compare (pseudo) 00212 f25, // Floating-point Compare (pseudo) 00213 f26, // Floating-point Compare (pseudo) 00214 f27; // Floating-point Parallel Compare (pseudo) 00215 00216 ISA_PACK_TYPE x1, // Floating-point Multiply Add 00217 x2, // Move Long Immediate_64 00218 x3, // Long Branch 00219 x4, // Long Call 00220 x5; // Long Branch (pseudo) 00221 00222 OPND_ADJ_TYPE comp6, 00223 no_adj, 00224 decr, 00225 incr, 00226 sext8_incr, 00227 sext8, 00228 comp5, 00229 pack_i1, 00230 unpack_i1, 00231 pack_m17, 00232 unpack_m17; 00233 00234 ISA_Pack_Begin("ia64", 41); 00235 00236 /* Create the various adjustments that need to be performed between 00237 * assembly language form and packed form. Note that simple shift 00238 * adjustments have been accomplished directly in the operand packing 00239 * specification. 00240 */ 00241 no_adj = Create_Operand_Adjustment("no adjustment", "O_VAL"); 00242 comp6 = Create_Operand_Adjustment("6-bit complement", "O_VAL ^ 0x3f"); 00243 decr = Create_Operand_Adjustment("decrement", "O_VAL - 1"); 00244 incr = Create_Operand_Adjustment("increment", "O_VAL + 1"); 00245 sext8_incr = Create_Operand_Adjustment("sign-extend(8)/increment", 00246 "((O_VAL << 56) >> 56) + 1"); 00247 sext8 = Create_Operand_Adjustment("sign-extend(8)", "(O_VAL << 56) >> 56"); 00248 comp5 = Create_Operand_Adjustment("5-bit complement", "O_VAL ^ 0x1f"); 00249 pack_i1 = Create_Operand_Adjustment("Pack (I1)", 00250 "(O_VAL == 0) ? 0 : (O_VAL == 7) ? 1 : (O_VAL == 15) ? 2 : 3"); 00251 unpack_i1 = Create_Operand_Adjustment("Unpack (I1)", 00252 "(O_VAL == 0) ? 0 : (O_VAL == 1) ? 7 : (O_VAL == 2) ? 15 : 16"); 00253 pack_m17 = Create_Operand_Adjustment("Pack (M17)", 00254 "((O_VAL < 0) * 4) + ((O_VAL & 1) ? 3 : (O_VAL & 4) ? 2 : (O_VAL & 8) ? 1 : 0)"); 00255 unpack_m17 = Create_Operand_Adjustment("unpack (M17)", 00256 "(((O_VAL >= 4) ? -1 : 1) * (((O_VAL & 3) == 3) ? 1 : 1 << (4 - (O_VAL & 3))))"); 00257 00258 /* ===== A1: Integer ALU -- Register-Register ===== */ 00259 a1 = ISA_Pack_Type_Create("a1"); 00260 Operand(0, 0, 0, 6); // qp 00261 Result(0, 6, 7); // r1 00262 Operand(1, 0, 13, 7); // r2 00263 Operand(2, 0, 20, 7); // r3 00264 Instruction_Pack_Group(a1, 00265 TOP_add, 0x10000000000ULL, 00266 TOP_add_1, 0x10008000000ULL, 00267 TOP_sub, 0x10028000000ULL, 00268 TOP_sub_1, 0x10020000000ULL, 00269 TOP_addp4, 0x10040000000ULL, 00270 TOP_and, 0x10060000000ULL, 00271 TOP_andcm, 0x10068000000ULL, 00272 TOP_or, 0x10070000000ULL, 00273 TOP_xor, 0x10078000000ULL, 00274 TOP_UNDEFINED); 00275 00276 /* ===== A2: Shift Left and Add ===== */ 00277 a2 = ISA_Pack_Type_Create("a2"); 00278 Operand(0, 0, 0, 6); // qp 00279 Result(0, 6, 7); // r1 00280 Operand(1, 0, 13, 7); // r2 00281 Adjust_Operand(2, decr, incr); // ct_2d = count_2 - 1 00282 Operand(2, 0, 27, 2); // ct_2d 00283 Operand(3, 0, 20, 7); // r3 00284 Instruction_Pack_Group(a2, 00285 TOP_shladd, 0x10080000000ULL, 00286 TOP_shladdp4, 0x100c0000000ULL, 00287 TOP_UNDEFINED); 00288 00289 /* ===== A3: Integer ALU -- Immediate_8-Register ===== */ 00290 a3 = ISA_Pack_Type_Create("a3"); 00291 Operand(0, 0, 0, 6); // qp 00292 Result(0, 6, 7); // r1 00293 Operand(1, 0, 13, 7); // imm_7b 00294 Operand(1, 7, 36, 1); // s 00295 Operand(2, 0, 20, 7); // r3 00296 Instruction_Pack_Group(a3, 00297 TOP_sub_i, 0x10128000000ULL, 00298 TOP_and_i, 0x10160000000ULL, 00299 TOP_andcm_i, 0x10168000000ULL, 00300 TOP_or_i, 0x10170000000ULL, 00301 TOP_xor_i, 0x10178000000ULL, 00302 TOP_UNDEFINED); 00303 00304 /* ===== A4: Add Immediate_14 ===== */ 00305 a4 = ISA_Pack_Type_Create("a4"); 00306 Operand(0, 0, 0, 6); // qp 00307 Result(0, 6, 7); // r1 00308 Operand(1, 0, 13, 7); // imm_7b 00309 Operand(1, 7, 27, 6); // imm_6d 00310 Operand(1, 13, 36, 1); // s 00311 Operand(2, 0, 20, 7); // r3 00312 Instruction_Pack_Group(a4, 00313 TOP_adds, 0x10800000000ULL, 00314 TOP_addp4_i, 0x10c00000000ULL, 00315 TOP_UNDEFINED); 00316 00317 /* ===== A5: Add Immediate_22 ===== */ 00318 a5 = ISA_Pack_Type_Create("a5"); 00319 Operand(0, 0, 0, 6); // qp 00320 Result(0, 6, 7); // r1 00321 Operand(1, 0, 13, 7); // imm_7b 00322 Operand(1, 7, 27, 9); // imm_9d 00323 Operand(1, 16, 22, 5); // imm_5c 00324 Operand(1, 21, 36, 1); // s 00325 Operand(2, 0, 20, 2); // r3 00326 Instruction_Pack_Group(a5, 00327 TOP_addl, 0x12000000000ULL, 00328 TOP_UNDEFINED); 00329 00330 /* ===== A6: Integer Compare -- Register-Register ===== */ 00331 a6 = ISA_Pack_Type_Create("a6"); 00332 Operand(0, 0, 0, 6); // qp 00333 Result(0, 6, 6); // p1 00334 Result(1, 27, 6); // p2 00335 Operand(1, 0, 13, 7); // r2 00336 Operand(2, 0, 20, 7); // r3 00337 Instruction_Pack_Group(a6, 00338 TOP_cmp_lt, 0x18000000000ULL, 00339 TOP_cmp_ltu, 0x1a000000000ULL, 00340 TOP_cmp_eq, 0x1c000000000ULL, 00341 TOP_cmp_lt_unc, 0x18000001000ULL, 00342 TOP_cmp_ltu_unc, 0x1a000001000ULL, 00343 TOP_cmp_eq_unc, 0x1c000001000ULL, 00344 TOP_cmp_eq_and, 0x18200000000ULL, 00345 TOP_cmp_eq_or, 0x1a200000000ULL, 00346 TOP_cmp_eq_or_andcm, 0x1c200000000ULL, 00347 TOP_cmp_ne_and, 0x18200001000ULL, 00348 TOP_cmp_ne_or, 0x1a200001000ULL, 00349 TOP_cmp_ne_or_andcm, 0x1c200001000ULL, 00350 TOP_cmp4_lt, 0x18400000000ULL, 00351 TOP_cmp4_ltu, 0x1a400000000ULL, 00352 TOP_cmp4_eq, 0x1c400000000ULL, 00353 TOP_cmp4_lt_unc, 0x18400001000ULL, 00354 TOP_cmp4_ltu_unc, 0x1a400001000ULL, 00355 TOP_cmp4_eq_unc, 0x1c400001000ULL, 00356 TOP_cmp4_eq_and, 0x18600000000ULL, 00357 TOP_cmp4_eq_or, 0x1a600000000ULL, 00358 TOP_cmp4_eq_or_andcm, 0x1c600000000ULL, 00359 TOP_cmp4_ne_and, 0x18600001000ULL, 00360 TOP_cmp4_ne_or, 0x1a600001000ULL, 00361 TOP_cmp4_ne_or_andcm, 0x1c600001000ULL, 00362 TOP_UNDEFINED); 00363 00364 /* ===== A7: Integer Compare to Zero -- Register ===== */ 00365 a7 = ISA_Pack_Type_Create("a7"); 00366 Operand(0, 0, 0, 6); // qp 00367 Result(0, 6, 6); // p1 00368 Result(1, 27, 6); // p2 00369 Operand(1, 0, 20, 7); // r3 00370 Instruction_Pack_Group(a7, 00371 TOP_cmp_z1_gt_and, 0x19000000000ULL, 00372 TOP_cmp_z1_gt_or, 0x1b000000000ULL, 00373 TOP_cmp_z1_gt_or_andcm, 0x1d000000000ULL, 00374 TOP_cmp_z1_le_and, 0x19000001000ULL, 00375 TOP_cmp_z1_le_or, 0x1b000001000ULL, 00376 TOP_cmp_z1_le_or_andcm, 0x1d000001000ULL, 00377 TOP_cmp_z1_ge_and, 0x19200000000ULL, 00378 TOP_cmp_z1_ge_or, 0x1b200000000ULL, 00379 TOP_cmp_z1_ge_or_andcm, 0x1d200000000ULL, 00380 TOP_cmp_z1_lt_and, 0x19200001000ULL, 00381 TOP_cmp_z1_lt_or, 0x1b200001000ULL, 00382 TOP_cmp_z1_lt_or_andcm, 0x1d200001000ULL, 00383 TOP_cmp4_z1_gt_and, 0x19400000000ULL, 00384 TOP_cmp4_z1_gt_or, 0x1b400000000ULL, 00385 TOP_cmp4_z1_gt_or_andcm,0x1d400000000ULL, 00386 TOP_cmp4_z1_le_and, 0x19400001000ULL, 00387 TOP_cmp4_z1_le_or, 0x1b400001000ULL, 00388 TOP_cmp4_z1_le_or_andcm,0x1d400001000ULL, 00389 TOP_cmp4_z1_ge_and, 0x19600000000ULL, 00390 TOP_cmp4_z1_ge_or, 0x1b600000000ULL, 00391 TOP_cmp4_z1_ge_or_andcm,0x1d600000000ULL, 00392 TOP_cmp4_z1_lt_and, 0x19600001000ULL, 00393 TOP_cmp4_z1_lt_or, 0x1b600001000ULL, 00394 TOP_cmp4_z1_lt_or_andcm,0x1d600001000ULL, 00395 TOP_UNDEFINED); 00396 00397 /* ===== A8a: Integer Compare -- Immediate-Register ===== */ 00398 a8a = ISA_Pack_Type_Create("a8a"); 00399 Operand(0, 0, 0, 6); // qp 00400 Result(0, 6, 6); // p1 00401 Result(1, 27, 6); // p2 00402 Operand(1, 0, 13, 7); // imm_7b 00403 Operand(1, 7, 36, 1); // s 00404 Operand(2, 0, 20, 7); // r3 00405 Instruction_Pack_Group(a8a, 00406 TOP_cmp_i_lt, 0x18800000000ULL, 00407 TOP_cmp_i_eq, 0x1c800000000ULL, 00408 TOP_cmp_i_lt_unc, 0x18800001000ULL, 00409 TOP_cmp_i_eq_unc, 0x1c800001000ULL, 00410 TOP_cmp_i_eq_and, 0x18a00000000ULL, 00411 TOP_cmp_i_eq_or, 0x1aa00000000ULL, 00412 TOP_cmp_i_eq_or_andcm, 0x1ca00000000ULL, 00413 TOP_cmp_i_ne_and, 0x18a00001000ULL, 00414 TOP_cmp_i_ne_or, 0x1aa00001000ULL, 00415 TOP_cmp_i_ne_or_andcm, 0x1ca00001000ULL, 00416 TOP_cmp4_i_lt, 0x18c00000000ULL, 00417 TOP_cmp4_i_eq, 0x1cc00000000ULL, 00418 TOP_cmp4_i_lt_unc, 0x18c00001000ULL, 00419 TOP_cmp4_i_eq_unc, 0x1cc00001000ULL, 00420 TOP_cmp4_i_eq_and, 0x18e00000000ULL, 00421 TOP_cmp4_i_eq_or, 0x1ae00000000ULL, 00422 TOP_cmp4_i_eq_or_andcm, 0x1ce00000000ULL, 00423 TOP_cmp4_i_ne_and, 0x18e00001000ULL, 00424 TOP_cmp4_i_ne_or, 0x1ae00001000ULL, 00425 TOP_cmp4_i_ne_or_andcm, 0x1ce00001000ULL, 00426 TOP_UNDEFINED); 00427 00428 /* ===== A8b: Integer Compare -- Immediate-Register ===== */ 00429 a8b = ISA_Pack_Type_Create("a8b"); 00430 Operand(0, 0, 0, 6); // qp 00431 Result(0, 6, 6); // p1 00432 Result(1, 27, 6); // p2 00433 Adjust_Operand(1, no_adj, sext8); // imm8 = sext(imm) (unpack only) 00434 Operand(1, 0, 13, 7); // imm_7b 00435 Operand(1, 7, 36, 1); // s 00436 Operand(2, 0, 20, 7); // r3 00437 Instruction_Pack_Group(a8b, 00438 TOP_cmp_i_ltu, 0x1a800000000ULL, 00439 TOP_cmp_i_ltu_unc, 0x1a800001000ULL, 00440 TOP_cmp4_i_ltu, 0x1ac00000000ULL, 00441 TOP_cmp4_i_ltu_unc, 0x1ac00001000ULL, 00442 TOP_UNDEFINED); 00443 00444 /* ===== A9: Multimedia ALU ===== */ 00445 a9 = ISA_Pack_Type_Create("a9"); 00446 Operand(0, 0, 0, 6); // qp 00447 Result(0, 6, 7); // r1 00448 Operand(1, 0, 13, 7); // r2 00449 Operand(2, 0, 20, 7); // r3 00450 Instruction_Pack_Group(a9, 00451 TOP_padd1, 0x10400000000ULL, 00452 TOP_padd2, 0x10600000000ULL, 00453 TOP_padd4, 0x11400000000ULL, 00454 TOP_padd1_sss, 0x10408000000ULL, 00455 TOP_padd2_sss, 0x10608000000ULL, 00456 TOP_padd1_uuu, 0x10410000000ULL, 00457 TOP_padd2_uuu, 0x10610000000ULL, 00458 TOP_padd1_uus, 0x10418000000ULL, 00459 TOP_padd2_uus, 0x10618000000ULL, 00460 TOP_psub1, 0x10420000000ULL, 00461 TOP_psub2, 0x10620000000ULL, 00462 TOP_psub4, 0x11420000000ULL, 00463 TOP_psub1_sss, 0x10428000000ULL, 00464 TOP_psub2_sss, 0x10628000000ULL, 00465 TOP_psub1_uuu, 0x10430000000ULL, 00466 TOP_psub2_uuu, 0x10630000000ULL, 00467 TOP_psub1_uus, 0x10438000000ULL, 00468 TOP_psub2_uus, 0x10638000000ULL, 00469 TOP_pavg1, 0x10450000000ULL, 00470 TOP_pavg2, 0x10650000000ULL, 00471 TOP_pavg1_raz, 0x10458000000ULL, 00472 TOP_pavg2_raz, 0x10658000000ULL, 00473 TOP_pavgsub1, 0x10470000000ULL, 00474 TOP_pavgsub2, 0x10670000000ULL, 00475 TOP_pcmp1_eq, 0x10520000000ULL, 00476 TOP_pcmp2_eq, 0x10720000000ULL, 00477 TOP_pcmp4_eq, 0x11520000000ULL, 00478 TOP_pcmp1_gt, 0x10528000000ULL, 00479 TOP_pcmp2_gt, 0x10728000000ULL, 00480 TOP_pcmp4_gt, 0x11528000000ULL, 00481 TOP_UNDEFINED); 00482 00483 /* ===== A10: Multimedia Shift and Add ===== */ 00484 a10 = ISA_Pack_Type_Create("a10"); 00485 Operand(0, 0, 0, 6); // qp 00486 Result(0, 6, 7); // r1 00487 Operand(1, 0, 13, 7); // r2 00488 Adjust_Operand(2, decr, incr); // ct_2d = count_2 - 1 00489 Operand(2, 0, 27, 2); // ct_2d 00490 Operand(3, 0, 20, 7); // r3 00491 Instruction_Pack_Group(a10, 00492 TOP_pshladd2, 0x10680000000ULL, 00493 TOP_pshradd2, 0x106c0000000ULL, 00494 TOP_UNDEFINED); 00495 00496 /* ===== A11: Move General Register (pseudo) ===== */ 00497 a11 = ISA_Pack_Type_Create("a11"); 00498 Operand(0, 0, 0, 6); // qp 00499 Result(0, 6, 7); // r1 00500 Operand(1, 0, 20, 7); // r3 00501 Instruction_Pack_Group(a11, 00502 TOP_mov, 0x10800000000ULL, 00503 TOP_UNDEFINED); 00504 00505 /* ===== A12: Move Immediate (pseudo) ===== */ 00506 a12 = ISA_Pack_Type_Create("a12"); 00507 Operand(0, 0, 0, 6); // qp 00508 Result(0, 6, 7); // r1 00509 Operand(1, 0, 13, 7); // imm_7b 00510 Operand(1, 7, 27, 9); // imm_9d 00511 Operand(1, 16, 22, 5); // imm_5c 00512 Operand(1, 21, 36, 1); // s 00513 Instruction_Pack_Group(a12, 00514 TOP_mov_i, 0x12000000000ULL, 00515 TOP_UNDEFINED); 00516 00517 /* ===== A13: Integer Compare -- Register-Register (pseudo) ===== */ 00518 a13 = ISA_Pack_Type_Create("a13"); 00519 Operand(0, 0, 0, 6); // qp 00520 Result(0, 6, 6); // p1 00521 Result(1, 27, 6); // p2 00522 Operand(1, 0, 13, 7); // r2 00523 Operand(2, 0, 20, 7); // r3 00524 Instruction_Pack_Group(a13, 00525 TOP_cmp_eq_andcm, 0x18200001000ULL, 00526 TOP_cmp_eq_orcm, 0x1a200001000ULL, 00527 TOP_cmp_ne_andcm, 0x18200000000ULL, 00528 TOP_cmp_ne_orcm, 0x1a200000000ULL, 00529 TOP_cmp4_eq_andcm, 0x18600001000ULL, 00530 TOP_cmp4_eq_orcm, 0x1a600001000ULL, 00531 TOP_cmp4_ne_andcm, 0x18600000000ULL, 00532 TOP_cmp4_ne_orcm, 0x1a600000000ULL, 00533 TOP_UNDEFINED); 00534 00535 /* ===== A14: Integer Compare -- Register-Register (pseudo) ===== */ 00536 // swapped preds 00537 a14 = ISA_Pack_Type_Create("a14"); 00538 Operand(0, 0, 0, 6); // qp 00539 Result(0, 27, 6); // p2 00540 Result(1, 6, 6); // p1 00541 Operand(1, 0, 13, 7); // r2 00542 Operand(2, 0, 20, 7); // r3 00543 Instruction_Pack_Group(a14, 00544 TOP_cmp_eq_and_orcm, 0x1c200001000ULL, 00545 TOP_cmp_ge, 0x18000000000ULL, 00546 TOP_cmp_ge_unc, 0x18000001000ULL, 00547 TOP_cmp_geu, 0x1a000000000ULL, 00548 TOP_cmp_geu_unc, 0x1a000001000ULL, 00549 TOP_cmp_ne_and_orcm, 0x1c200000000ULL, 00550 TOP_cmp_ne, 0x1c000000000ULL, 00551 TOP_cmp_ne_unc, 0x1c000001000ULL, 00552 TOP_cmp4_eq_and_orcm, 0x1c600001000ULL, 00553 TOP_cmp4_ge, 0x18400000000ULL, 00554 TOP_cmp4_ge_unc, 0x18400001000ULL, 00555 TOP_cmp4_geu, 0x1a400000000ULL, 00556 TOP_cmp4_geu_unc, 0x1a400001000ULL, 00557 TOP_cmp4_ne_and_orcm, 0x1c600000000ULL, 00558 TOP_cmp4_ne, 0x1c400000000ULL, 00559 TOP_cmp4_ne_unc, 0x1c400001000ULL, 00560 TOP_UNDEFINED); 00561 00562 /* ===== A15: Integer Compare -- Register-Register (pseudo) ===== */ 00563 // swapped args 00564 a15 = ISA_Pack_Type_Create("a15"); 00565 Operand(0, 0, 0, 6); // qp 00566 Result(0, 6, 6); // p1 00567 Result(1, 27, 6); // p2 00568 Operand(1, 0, 20, 7); // r3 00569 Operand(2, 0, 13, 7); // r2 00570 Instruction_Pack_Group(a15, 00571 TOP_cmp_gt, 0x18000000000ULL, 00572 TOP_cmp_gt_unc, 0x18000001000ULL, 00573 TOP_cmp_gtu, 0x1a000000000ULL, 00574 TOP_cmp_gtu_unc, 0x1a000001000ULL, 00575 TOP_cmp4_gt, 0x18400000000ULL, 00576 TOP_cmp4_gt_unc, 0x18400001000ULL, 00577 TOP_cmp4_gtu, 0x1a400000000ULL, 00578 TOP_cmp4_gtu_unc, 0x1a400001000ULL, 00579 TOP_UNDEFINED); 00580 00581 /* ===== A16: Integer Compare -- Register-Register (pseudo) ===== */ 00582 // swapped preds and args 00583 a16 = ISA_Pack_Type_Create("a16"); 00584 Operand(0, 0, 0, 6); // qp 00585 Result(0, 27, 6); // p2 00586 Result(1, 6, 6); // p1 00587 Operand(1, 0, 20, 7); // r3 00588 Operand(2, 0, 13, 7); // r2 00589 Instruction_Pack_Group(a16, 00590 TOP_cmp_le, 0x18000000000ULL, 00591 TOP_cmp_le_unc, 0x18000001000ULL, 00592 TOP_cmp_leu, 0x1a000000000ULL, 00593 TOP_cmp_leu_unc, 0x1a000001000ULL, 00594 TOP_cmp4_le, 0x18400000000ULL, 00595 TOP_cmp4_le_unc, 0x18400001000ULL, 00596 TOP_cmp4_leu, 0x1a400000000ULL, 00597 TOP_cmp4_leu_unc, 0x1a400001000ULL, 00598 TOP_UNDEFINED); 00599 00600 /* ===== A17: Integer Compare -- Immediate-Register (pseudo) ===== */ 00601 a17 = ISA_Pack_Type_Create("a17"); 00602 Operand(0, 0, 0, 6); // qp 00603 Result(0, 6, 6); // p1 00604 Result(1, 27, 6); // p2 00605 Operand(1, 0, 13, 7); // imm_7b 00606 Operand(1, 7, 36, 1); // s 00607 Operand(2, 0, 20, 7); // r3 00608 Instruction_Pack_Group(a17, 00609 TOP_cmp_i_eq_andcm, 0x18a00001000ULL, 00610 TOP_cmp_i_eq_orcm, 0x1aa00001000ULL, 00611 TOP_cmp_i_ne_andcm, 0x18a00000000ULL, 00612 TOP_cmp_i_ne_orcm, 0x1aa00000000ULL, 00613 TOP_cmp4_i_eq_andcm, 0x18e00001000ULL, 00614 TOP_cmp4_i_eq_orcm, 0x1ae00001000ULL, 00615 TOP_cmp4_i_ne_andcm, 0x18e00000000ULL, 00616 TOP_cmp4_i_ne_orcm, 0x1ae00000000ULL, 00617 TOP_UNDEFINED); 00618 00619 /* ===== A18: Integer Compare -- Immediate-Register (pseudo) ===== */ 00620 // swapped preds 00621 a18 = ISA_Pack_Type_Create("a18"); 00622 Operand(0, 0, 0, 6); // qp 00623 Result(0, 27, 6); // p2 00624 Result(1, 6, 6); // p1 00625 Operand(1, 0, 13, 7); // imm_7b 00626 Operand(1, 7, 36, 1); // s 00627 Operand(2, 0, 20, 7); // r3 00628 Instruction_Pack_Group(a18, 00629 TOP_cmp_i_eq_and_orcm, 0x1ca00001000ULL, 00630 TOP_cmp_i_ge, 0x18800000000ULL, 00631 TOP_cmp_i_ge_unc, 0x18800001000ULL, 00632 TOP_cmp_i_ne_and_orcm, 0x1ca00000000ULL, 00633 TOP_cmp_i_ne, 0x1c800000000ULL, 00634 TOP_cmp_i_ne_unc, 0x1c800001000ULL, 00635 TOP_cmp4_i_eq_and_orcm, 0x1ce00001000ULL, 00636 TOP_cmp4_i_ge, 0x18c00000000ULL, 00637 TOP_cmp4_i_ge_unc, 0x18c00001000ULL, 00638 TOP_cmp4_i_ne_and_orcm, 0x1ce00000000ULL, 00639 TOP_cmp4_i_ne, 0x1cc00000000ULL, 00640 TOP_cmp4_i_ne_unc, 0x1cc00001000ULL, 00641 TOP_UNDEFINED); 00642 00643 /* ===== A19: Integer Compare -- Immediate-Register (pseudo) ===== */ 00644 // swapped preds and sext(immed) 00645 a19 = ISA_Pack_Type_Create("a19"); 00646 Operand(0, 0, 0, 6); // qp 00647 Result(0, 27, 6); // p2 00648 Result(1, 6, 6); // p1 00649 Adjust_Operand(1, no_adj, sext8); // imm8 = sext(imm) (unpack only) 00650 Operand(1, 0, 13, 7); // imm_7b 00651 Operand(1, 7, 36, 1); // s 00652 Operand(2, 0, 20, 7); // r3 00653 Instruction_Pack_Group(a19, 00654 TOP_cmp_i_geu, 0x1a800000000ULL, 00655 TOP_cmp_i_geu_unc, 0x1a800001000ULL, 00656 TOP_cmp4_i_geu, 0x1ac00000000ULL, 00657 TOP_cmp4_i_geu_unc, 0x1ac00001000ULL, 00658 TOP_UNDEFINED); 00659 00660 /* ===== A20: Integer Compare -- Immediate-Register (pseudo) ===== */ 00661 // immed-1 00662 a20 = ISA_Pack_Type_Create("a20"); 00663 Operand(0, 0, 0, 6); // qp 00664 Result(0, 6, 6); // p1 00665 Result(1, 27, 6); // p2 00666 Adjust_Operand(1, decr, sext8_incr); // imm_8 = imm_8 - 1 00667 Operand(1, 0, 13, 7); // imm_7b 00668 Operand(1, 7, 36, 1); // s 00669 Operand(2, 0, 20, 7); // r3 00670 Instruction_Pack_Group(a20, 00671 TOP_cmp_i_le, 0x18800000000ULL, 00672 TOP_cmp_i_le_unc, 0x18800001000ULL, 00673 TOP_cmp_i_leu, 0x1a800000000ULL, 00674 TOP_cmp_i_leu_unc, 0x1a800001000ULL, 00675 TOP_cmp4_i_le, 0x18c00000000ULL, 00676 TOP_cmp4_i_le_unc, 0x18c00001000ULL, 00677 TOP_cmp4_i_leu, 0x1ac00000000ULL, 00678 TOP_cmp4_i_leu_unc, 0x1ac00001000ULL, 00679 TOP_UNDEFINED); 00680 00681 /* ===== A21: Integer Compare -- Immediate-Register (pseudo) ===== */ 00682 // swapped pred and immed-1 00683 a21 = ISA_Pack_Type_Create("a21"); 00684 Operand(0, 0, 0, 6); // qp 00685 Result(0, 27, 6); // p2 00686 Result(1, 6, 6); // p1 00687 Adjust_Operand(1, decr, sext8_incr); // imm_8 = imm_8 - 1 00688 Operand(1, 0, 13, 7); // imm_7b 00689 Operand(1, 7, 36, 1); // s 00690 Operand(2, 0, 20, 7); // r3 00691 Instruction_Pack_Group(a21, 00692 TOP_cmp_i_gt, 0x18800000000ULL, 00693 TOP_cmp_i_gt_unc, 0x18800001000ULL, 00694 TOP_cmp_i_gtu, 0x1a800000000ULL, 00695 TOP_cmp_i_gtu_unc, 0x1a800001000ULL, 00696 TOP_cmp4_i_gt, 0x18c00000000ULL, 00697 TOP_cmp4_i_gt_unc, 0x18c00001000ULL, 00698 TOP_cmp4_i_gtu, 0x1ac00000000ULL, 00699 TOP_cmp4_i_gtu_unc, 0x1ac00001000ULL, 00700 TOP_UNDEFINED); 00701 00702 /* ===== A22: Integer Compare to Zero -- Register (pseudo) ===== */ 00703 // swapped preds 00704 a22 = ISA_Pack_Type_Create("a22"); 00705 Operand(0, 0, 0, 6); // qp 00706 Result(0, 27, 6); // p2 00707 Result(1, 6, 6); // p1 00708 Operand(1, 0, 20, 7); // r3 00709 Instruction_Pack_Group(a22, 00710 TOP_cmp_z1_gt_and_orcm, 0x1d000001000ULL, 00711 TOP_cmp_z1_le_and_orcm, 0x1d000000000ULL, 00712 TOP_cmp_z1_ge_and_orcm, 0x1d200001000ULL, 00713 TOP_cmp_z1_lt_and_orcm, 0x1d200000000ULL, 00714 TOP_cmp4_z1_gt_and_orcm,0x1d400001000ULL, 00715 TOP_cmp4_z1_le_and_orcm,0x1d400000000ULL, 00716 TOP_cmp4_z1_ge_and_orcm,0x1d600001000ULL, 00717 TOP_cmp4_z1_lt_and_orcm,0x1d600000000ULL, 00718 TOP_cmp_z2_gt_and_orcm, 0x1d200000000ULL, 00719 TOP_cmp_z2_le_and_orcm, 0x1d200001000ULL, 00720 TOP_cmp_z2_ge_and_orcm, 0x1d000000000ULL, 00721 TOP_cmp_z2_lt_and_orcm, 0x1d000001000ULL, 00722 TOP_cmp4_z2_gt_and_orcm,0x1d600000000ULL, 00723 TOP_cmp4_z2_le_and_orcm,0x1d600001000ULL, 00724 TOP_cmp4_z2_ge_and_orcm,0x1d400000000ULL, 00725 TOP_cmp4_z2_lt_and_orcm,0x1d400001000ULL, 00726 TOP_UNDEFINED); 00727 00728 /* ===== A23: Integer Compare to Zero -- Register (pseudo) ===== */ 00729 a23 = ISA_Pack_Type_Create("a23"); 00730 Operand(0, 0, 0, 6); // qp 00731 Result(0, 6, 6); // p1 00732 Result(1, 27, 6); // p2 00733 Operand(1, 0, 20, 7); // r3 00734 Instruction_Pack_Group(a23, 00735 TOP_cmp_z1_gt_andcm, 0x19000001000ULL, 00736 TOP_cmp_z1_gt_orcm, 0x1b000001000ULL, 00737 TOP_cmp_z1_le_andcm, 0x19000000000ULL, 00738 TOP_cmp_z1_le_orcm, 0x1b000000000ULL, 00739 TOP_cmp_z1_ge_andcm, 0x19200001000ULL, 00740 TOP_cmp_z1_ge_orcm, 0x1b200001000ULL, 00741 TOP_cmp_z1_lt_andcm, 0x19200000000ULL, 00742 TOP_cmp_z1_lt_orcm, 0x1b200000000ULL, 00743 TOP_cmp4_z1_gt_andcm, 0x19400001000ULL, 00744 TOP_cmp4_z1_gt_orcm, 0x1b400001000ULL, 00745 TOP_cmp4_z1_le_andcm, 0x19400000000ULL, 00746 TOP_cmp4_z1_le_orcm, 0x1b400000000ULL, 00747 TOP_cmp4_z1_ge_andcm, 0x19600001000ULL, 00748 TOP_cmp4_z1_ge_orcm, 0x1b600001000ULL, 00749 TOP_cmp4_z1_lt_andcm, 0x19600000000ULL, 00750 TOP_cmp4_z1_lt_orcm, 0x1b600000000ULL, 00751 TOP_cmp_z2_gt_andcm, 0x19200000000ULL, 00752 TOP_cmp_z2_gt_orcm, 0x1b200000000ULL, 00753 TOP_cmp_z2_le_andcm, 0x19200001000ULL, 00754 TOP_cmp_z2_le_orcm, 0x1b200001000ULL, 00755 TOP_cmp_z2_ge_andcm, 0x19000000000ULL, 00756 TOP_cmp_z2_ge_orcm, 0x1b000000000ULL, 00757 TOP_cmp_z2_lt_andcm, 0x19000001000ULL, 00758 TOP_cmp_z2_lt_orcm, 0x1b000001000ULL, 00759 TOP_cmp4_z2_gt_andcm, 0x19600000000ULL, 00760 TOP_cmp4_z2_gt_orcm, 0x1b600000000ULL, 00761 TOP_cmp4_z2_le_andcm, 0x19600001000ULL, 00762 TOP_cmp4_z2_le_orcm, 0x1b600001000ULL, 00763 TOP_cmp4_z2_ge_andcm, 0x19400000000ULL, 00764 TOP_cmp4_z2_ge_orcm, 0x1b400000000ULL, 00765 TOP_cmp4_z2_lt_andcm, 0x19400001000ULL, 00766 TOP_cmp4_z2_lt_orcm, 0x1b400001000ULL, 00767 TOP_cmp_z2_gt_and, 0x19200001000ULL, 00768 TOP_cmp_z2_gt_or, 0x1b200001000ULL, 00769 TOP_cmp_z2_gt_or_andcm, 0x1d200001000ULL, 00770 TOP_cmp_z2_le_and, 0x19200000000ULL, 00771 TOP_cmp_z2_le_or, 0x1b200000000ULL, 00772 TOP_cmp_z2_le_or_andcm, 0x1d200000000ULL, 00773 TOP_cmp_z2_ge_and, 0x19000001000ULL, 00774 TOP_cmp_z2_ge_or, 0x1b000001000ULL, 00775 TOP_cmp_z2_ge_or_andcm, 0x1d000001000ULL, 00776 TOP_cmp_z2_lt_and, 0x19000000000ULL, 00777 TOP_cmp_z2_lt_or, 0x1b000000000ULL, 00778 TOP_cmp_z2_lt_or_andcm, 0x1d000000000ULL, 00779 TOP_cmp4_z2_gt_and, 0x19600001000ULL, 00780 TOP_cmp4_z2_gt_or, 0x1b600001000ULL, 00781 TOP_cmp4_z2_gt_or_andcm,0x1d600001000ULL, 00782 TOP_cmp4_z2_le_and, 0x19600000000ULL, 00783 TOP_cmp4_z2_le_or, 0x1b600000000ULL, 00784 TOP_cmp4_z2_le_or_andcm,0x1d600000000ULL, 00785 TOP_cmp4_z2_ge_and, 0x19400001000ULL, 00786 TOP_cmp4_z2_ge_or, 0x1b400001000ULL, 00787 TOP_cmp4_z2_ge_or_andcm,0x1d400001000ULL, 00788 TOP_cmp4_z2_lt_and, 0x19400000000ULL, 00789 TOP_cmp4_z2_lt_or, 0x1b400000000ULL, 00790 TOP_cmp4_z2_lt_or_andcm,0x1d400000000ULL, 00791 TOP_UNDEFINED); 00792 00793 /* ===== I1: Multimedia Multiply and Shift ===== */ 00794 i1 = ISA_Pack_Type_Create("i1"); 00795 Operand(0, 0, 0, 6); // qp 00796 Result(0, 6, 7); // r1 00797 Operand(1, 0, 13, 7); // r2 00798 Operand(2, 0, 20, 7); // r3 00799 Adjust_Operand(3, pack_i1, unpack_i1); // ct_2d = (count_2 == 0) ? 0 : (count_2 == 7) ? 1 : (count_2 == 15) ? 2 : 3 00800 Operand(3, 0, 30, 2); // ct_2d 00801 Instruction_Pack_Group(i1, 00802 TOP_pmpyshr2, 0x0e230000000ULL, 00803 TOP_pmpyshr2_u, 0x0e210000000ULL, 00804 TOP_UNDEFINED); 00805 00806 /* ===== I2: Multimedia Multiply/Mix/Pack/Unpack ===== */ 00807 i2 = ISA_Pack_Type_Create("i2"); 00808 Operand(0, 0, 0, 6); // qp 00809 Result(0, 6, 7); // r1 00810 Operand(1, 0, 13, 7); // r2 00811 Operand(2, 0, 20, 7); // r3 00812 Instruction_Pack_Group(i2, 00813 TOP_pmpy2_r, 0x0ead0000000ULL, 00814 TOP_pmpy2_l, 0x0eaf0000000ULL, 00815 TOP_mix1_r, 0x0e880000000ULL, 00816 TOP_mix2_r, 0x0ea80000000ULL, 00817 TOP_mix4_r, 0x0f880000000ULL, 00818 TOP_mix1_l, 0x0e8a0000000ULL, 00819 TOP_mix2_l, 0x0eaa0000000ULL, 00820 TOP_mix4_l, 0x0f8a0000000ULL, 00821 TOP_pack2_uss, 0x0ea00000000ULL, 00822 TOP_pack2_sss, 0x0ea20000000ULL, 00823 TOP_pack4_sss, 0x0f820000000ULL, 00824 TOP_unpack1_h, 0x0e840000000ULL, 00825 TOP_unpack2_h, 0x0ea40000000ULL, 00826 TOP_unpack4_h, 0x0f840000000ULL, 00827 TOP_unpack1_l, 0x0e860000000ULL, 00828 TOP_unpack2_l, 0x0ea60000000ULL, 00829 TOP_unpack4_l, 0x0f860000000ULL, 00830 TOP_pmin1_u, 0x0e810000000ULL, 00831 TOP_pmax1_u, 0x0e850000000ULL, 00832 TOP_pmin2, 0x0ea30000000ULL, 00833 TOP_pmax2, 0x0ea70000000ULL, 00834 TOP_psad1, 0x0e8b0000000ULL, 00835 TOP_UNDEFINED); 00836 00837 /* ===== I3: Multimedia Mux1 ===== */ 00838 i3 = ISA_Pack_Type_Create("i3"); 00839 Operand(0, 0, 0, 6); // qp 00840 Result(0, 6, 7); // r1 00841 Operand(1, 0, 13, 7); // r2 00842 Operand(2, 0, 20, 4); // mbt_4c 00843 Instruction_Pack_Group(i3, 00844 TOP_mux1, 0x0eca0000000ULL, 00845 TOP_UNDEFINED); 00846 00847 /* ===== I4: Multimedia Mux2 ===== */ 00848 i4 = ISA_Pack_Type_Create("i4"); 00849 Operand(0, 0, 0, 6); // qp 00850 Result(0, 6, 7); // r1 00851 Operand(1, 0, 13, 7); // r2 00852 Operand(2, 0, 20, 8); // mht_8c 00853 Instruction_Pack_Group(i4, 00854 TOP_mux2, 0x0eea0000000ULL, 00855 TOP_UNDEFINED); 00856 00857 /* ===== I5: Shift Right -- Variable ===== */ 00858 i5 = ISA_Pack_Type_Create("i5"); 00859 Operand(0, 0, 0, 6); // qp 00860 Result(0, 6, 7); // r1 00861 Operand(1, 0, 20, 7); // r3 00862 Operand(2, 0, 13, 7); // r2 00863 Instruction_Pack_Group(i5, 00864 TOP_pshr2, 0x0e220000000ULL, 00865 TOP_pshr4, 0x0f020000000ULL, 00866 TOP_shr, 0x0f220000000ULL, 00867 TOP_pshr2_u, 0x0e200000000ULL, 00868 TOP_pshr4_u, 0x0f000000000ULL, 00869 TOP_shr_u, 0x0f200000000ULL, 00870 TOP_UNDEFINED); 00871 00872 /* ===== I6: Multimedia Shift Right -- Fixed ===== */ 00873 i6 = ISA_Pack_Type_Create("i6"); 00874 Operand(0, 0, 0, 6); // qp 00875 Result(0, 6, 7); // r1 00876 Operand(1, 0, 20, 7); // r3 00877 Operand(2, 0, 14, 5); // count_5b 00878 Instruction_Pack_Group(i6, 00879 TOP_pshr2_i, 0x0e630000000ULL, 00880 TOP_pshr4_i, 0x0f430000000ULL, 00881 TOP_pshr2_i_u, 0x0e610000000ULL, 00882 TOP_pshr4_i_u, 0x0f410000000ULL, 00883 TOP_UNDEFINED); 00884 00885 /* ===== I7: Shift Left -- Variable ===== */ 00886 i7 = ISA_Pack_Type_Create("i7"); 00887 Operand(0, 0, 0, 6); // qp 00888 Result(0, 6, 7); // r1 00889 Operand(1, 0, 13, 7); // r2 00890 Operand(2, 0, 20, 7); // r3 00891 Instruction_Pack_Group(i7, 00892 TOP_pshl2, 0x0e240000000ULL, 00893 TOP_pshl4, 0x0f040000000ULL, 00894 TOP_shl, 0x0f240000000ULL, 00895 TOP_UNDEFINED); 00896 00897 /* ===== I8: Multimedia Shift Left -- Fixed ===== */ 00898 i8 = ISA_Pack_Type_Create("i8"); 00899 Operand(0, 0, 0, 6); // qp 00900 Result(0, 6, 7); // r1 00901 Operand(1, 0, 13, 7); // r2 00902 Adjust_Operand(2, comp5, comp5); // ccount_5b = 31 - count_5 00903 Operand(2, 0, 20, 5); // ccount_5b 00904 Instruction_Pack_Group(i8, 00905 TOP_pshl2_i, 0x0ee50000000ULL, 00906 TOP_pshl4_i, 0x0fc50000000ULL, 00907 TOP_UNDEFINED); 00908 00909 /* ===== I9: Population Count ===== */ 00910 i9 = ISA_Pack_Type_Create("i9"); 00911 Operand(0, 0, 0, 6); // qp 00912 Result(0, 6, 7); // r1 00913 Operand(1, 0, 20, 7); // r3 00914 Instruction_Pack_Group(i9, 00915 TOP_popcnt, 0x0e690000000ULL, 00916 TOP_UNDEFINED); 00917 00918 /* ===== I10: Shift Right Pair ===== */ 00919 i10 = ISA_Pack_Type_Create("i10"); 00920 Operand(0, 0, 0, 6); // qp 00921 Result(0, 6, 7); // r1 00922 Operand(1, 0, 13, 7); // r2 00923 Operand(2, 0, 20, 7); // r3 00924 Operand(3, 0, 27, 6); // count_6d 00925 Instruction_Pack_Group(i10, 00926 TOP_shrp, 0x0ac00000000ULL, 00927 TOP_UNDEFINED); 00928 00929 /* ===== I11: Extract ===== */ 00930 i11 = ISA_Pack_Type_Create("i11"); 00931 Operand(0, 0, 0, 6); // qp 00932 Result(0, 6, 7); // r1 00933 Operand(1, 0, 20, 7); // r3 00934 Operand(2, 0, 14, 6); // pos_6b 00935 Adjust_Operand(3, decr, incr); // len_6d = len_6 - 1 00936 Operand(3, 0, 27, 6); // len_6d 00937 Instruction_Pack_Group(i11, 00938 TOP_extr_u, 0x0a400000000ULL, 00939 TOP_extr, 0x0a400002000ULL, 00940 TOP_UNDEFINED); 00941 00942 /* ===== I12: Zero and Deposit ===== */ 00943 i12 = ISA_Pack_Type_Create("i12"); 00944 Operand(0, 0, 0, 6); // qp 00945 Result(0, 6, 7); // r1 00946 Operand(1, 0, 13, 7); // r2 00947 Adjust_Operand(2, comp6, comp6); // cpos_6c = 63 - pos_6 00948 Operand(2, 0, 20, 6); // cpos_6c 00949 Adjust_Operand(3, decr, incr); // len_6d = len_6 - 1 00950 Operand(3, 0, 27, 6); // len_6d 00951 Instruction_Pack_Group(i12, 00952 TOP_dep_z, 0x0a600000000ULL, 00953 TOP_UNDEFINED); 00954 00955 /* ===== I13: Zero and Deposit Immediate_8 ===== */ 00956 i13 = ISA_Pack_Type_Create("i13"); 00957 Operand(0, 0, 0, 6); // qp 00958 Result(0, 6, 7); // r1 00959 Operand(1, 0, 13, 7); // imm_7b 00960 Operand(1, 7, 36, 1); // s 00961 Adjust_Operand(2, comp6, comp6); // cpos_6c = 63 - pos_6 00962 Operand(2, 0, 20, 6); // cpos_6c 00963 Adjust_Operand(3, decr, incr); // len_6d = len_6 - 1 00964 Operand(3, 0, 27, 6); // len_6d 00965 Instruction_Pack_Group(i13, 00966 TOP_dep_i_z, 0x0a604000000ULL, 00967 TOP_UNDEFINED); 00968 00969 /* ===== I14: Deposit Immediate_1 ===== */ 00970 i14 = ISA_Pack_Type_Create("i14"); 00971 Operand(0, 0, 0, 6); // qp 00972 Result(0, 6, 7); // r1 00973 Operand(1, 0, 36, 1); // s 00974 Operand(2, 0, 20, 7); // r3 00975 Adjust_Operand(3, comp6, comp6); // cpos_6b = 63 - pos_6 00976 Operand(3, 0, 14, 6); // cpos_6b 00977 Adjust_Operand(4, decr, incr); // len_6d = len_6 - 1; 00978 Operand(4, 0, 27, 6); // len_6d 00979 Instruction_Pack_Group(i14, 00980 TOP_dep_i, 0x0ae00000000ULL, 00981 TOP_UNDEFINED); 00982 00983 /* ===== I15: Deposit ===== */ 00984 i15 = ISA_Pack_Type_Create("i15"); 00985 Operand(0, 0, 0, 6); // qp 00986 Result(0, 6, 7); // r1 00987 Operand(1, 0, 13, 7); // r2 00988 Operand(2, 0, 20, 7); // r3 00989 Adjust_Operand(3, comp6, comp6); // cpos_6b = 63 - pos_6 00990 Operand(3, 0, 31, 6); // cpos_6d 00991 Adjust_Operand(4, decr, incr); // len_4d = len_4 - 1; 00992 Operand(4, 0, 27, 4); // len_4d 00993 Instruction_Pack_Group(i15, 00994 TOP_dep, 0x08000000000ULL, 00995 TOP_UNDEFINED); 00996 00997 /* ===== I16: Test Bit ===== */ 00998 i16 = ISA_Pack_Type_Create("i16"); 00999 Operand(0, 0, 0, 6); // qp 01000 Result(0, 6, 6); // p1 01001 Result(1, 27, 6); // p2 01002 Operand(1, 0, 20, 7); // r3 01003 Operand(2, 0, 14, 6); // pos_6b 01004 Instruction_Pack_Group(i16, 01005 TOP_tbit_z, 0x0a000000000ULL, 01006 TOP_tbit_z_unc, 0x0a000001000ULL, 01007 TOP_tbit_z_and, 0x0b000000000ULL, 01008 TOP_tbit_nz_and, 0x0b000001000ULL, 01009 TOP_tbit_z_or, 0x0a200000000ULL, 01010 TOP_tbit_nz_or, 0x0a200001000ULL, 01011 TOP_tbit_z_or_andcm, 0x0b200000000ULL, 01012 TOP_tbit_nz_or_andcm, 0x0b200001000ULL, 01013 TOP_UNDEFINED); 01014 01015 /* ===== I17: Test NaT ===== */ 01016 i17 = ISA_Pack_Type_Create("i17"); 01017 Operand(0, 0, 0, 6); // qp 01018 Result(0, 6, 6); // p1 01019 Result(1, 27, 6); // p2 01020 Operand(1, 0, 20, 7); // r3 01021 Instruction_Pack_Group(i17, 01022 TOP_tnat_z, 0x0a000002000ULL, 01023 TOP_tnat_z_unc, 0x0a000003000ULL, 01024 TOP_tnat_z_and, 0x0b000002000ULL, 01025 TOP_tnat_nz_and, 0x0b000003000ULL, 01026 TOP_tnat_z_or, 0x0a200002000ULL, 01027 TOP_tnat_nz_or, 0x0a200003000ULL, 01028 TOP_tnat_z_or_andcm, 0x0b200002000ULL, 01029 TOP_tnat_nz_or_andcm, 0x0b200003000ULL, 01030 TOP_UNDEFINED); 01031 01032 /* ===== I19: Break/Nop ===== */ 01033 i19 = ISA_Pack_Type_Create("i19"); 01034 Operand(0, 0, 0, 6); // qp 01035 Operand(1, 0, 6, 20); // imm_20a 01036 Operand(1, 20, 36, 1); // i 01037 Instruction_Pack_Group(i19, 01038 TOP_break_i, 0x00000000000ULL, 01039 TOP_nop_i, 0x00008000000ULL, 01040 TOP_UNDEFINED); 01041 01042 /* ===== I20: Integer Speculation Check ===== */ 01043 i20 = ISA_Pack_Type_Create("i20"); 01044 Operand(0, 0, 0, 6); // qp 01045 Operand(1, 0, 13, 7); // r2 01046 // Adjust_Operand(2, shr4, shl4); // imm_21 = target_25 >> 4 01047 Operand(2, 4, 6, 7); // imm_7a 01048 Operand(2, 11, 20, 13); // imm_13c 01049 Operand(2, 24, 36, 1); // s 01050 Instruction_Pack_Group(i20, 01051 TOP_chk_s_i, 0x00200000000ULL, 01052 TOP_UNDEFINED); 01053 01054 /* ===== I21: Move to BR ===== */ 01055 i21 = ISA_Pack_Type_Create("i21"); 01056 Operand(0, 0, 0, 6); // qp 01057 Operand(1, 0, 20, 2); // mwh 01058 Operand(2, 0, 23, 1); // ih 01059 Result(0, 6, 3); // b1 01060 Operand(3, 0, 13, 7); // r2 01061 // Adjust_Operand(4, shr4, shl4); // timm_9c = tag_13 >> 4 01062 Operand(4, 4, 24, 9); // timm_9c 01063 Instruction_Pack_Group(i21, 01064 TOP_mov_t_br_i, 0x00e00000000ULL, 01065 TOP_mov_t_br_ret, 0x00e00400000ULL, 01066 TOP_UNDEFINED); 01067 01068 /* ===== I22: Move from BR ===== */ 01069 i22 = ISA_Pack_Type_Create("i22"); 01070 Operand(0, 0, 0, 6); // qp 01071 Result(0, 6, 7); // r1 01072 Operand(1, 0, 13, 3); // b2 01073 Instruction_Pack_Group(i22, 01074 TOP_mov_f_br, 0x00188000000ULL, 01075 TOP_UNDEFINED); 01076 01077 /* ===== I23: Move to Predicates -- Register ===== */ 01078 i23 = ISA_Pack_Type_Create("i23"); 01079 Operand(0, 0, 0, 6); // qp 01080 Operand(1, 0, 13, 7); // r2 01081 // Adjust_Operand(2, shr1, shl1); // mask_16 = mask_17 >> 1 01082 Operand(2, 1, 6, 7); // mask_7a 01083 Operand(2, 8, 24, 8); // mask_8c 01084 Operand(2, 16, 36, 1); // s 01085 Instruction_Pack_Group(i23, 01086 TOP_mov_t_pr, 0x00600000000ULL, 01087 TOP_UNDEFINED); 01088 01089 /* ===== I24: Move to Predicates -- Immediate_44 ===== */ 01090 i24 = ISA_Pack_Type_Create("i24"); 01091 Operand(0, 0, 0, 6); // qp 01092 // Adjust_Operand(1, shr16, shl16); // imm_28 = imm_44 >> 16 01093 Operand(1, 16, 6, 27); // imm_27a 01094 Operand(1, 43, 36, 1); // s 01095 Instruction_Pack_Group(i24, 01096 TOP_mov_t_pr_i, 0x00400000000ULL, 01097 TOP_UNDEFINED); 01098 01099 /* ===== I25: Move from Predicates/IP ===== */ 01100 i25 = ISA_Pack_Type_Create("i25"); 01101 Operand(0, 0, 0, 6); // qp 01102 Result(0, 6, 7); // r1 01103 Instruction_Pack_Group(i25, 01104 TOP_mov_f_ip, 0x00180000000ULL, 01105 TOP_mov_f_pr, 0x00198000000ULL, 01106 TOP_UNDEFINED); 01107 01108 /* ===== I26: Move to AR -- Register ===== */ 01109 i26 = ISA_Pack_Type_Create("i26"); 01110 Operand(0, 0, 0, 6); // qp 01111 Result(0, 20, 7); // ar3 01112 Operand(1, 0, 13, 7); // r2 01113 Instruction_Pack_Group(i26, 01114 TOP_mov_t_ar_r_i, 0x00150000000ULL, 01115 TOP_UNDEFINED); 01116 01117 /* ===== I27: Move to AR -- Immediate_8 ===== */ 01118 i27 = ISA_Pack_Type_Create("i27"); 01119 Operand(0, 0, 0, 6); // qp 01120 Result(0, 20, 7); // ar3 01121 Operand(1, 0, 13, 7); // imm_7b 01122 Operand(1, 7, 36, 1); // s 01123 Instruction_Pack_Group(i27, 01124 TOP_mov_t_ar_i_i, 0x00050000000ULL, 01125 TOP_UNDEFINED); 01126 01127 /* ===== I28: Move from AR ===== */ 01128 i28 = ISA_Pack_Type_Create("i28"); 01129 Operand(0, 0, 0, 6); // qp 01130 Result(0, 6, 7); // r1 01131 Operand(1, 0, 20, 7); // ar3 01132 Instruction_Pack_Group(i28, 01133 TOP_mov_f_ar_i, 0x00190000000ULL, 01134 TOP_UNDEFINED); 01135 01136 /* ===== I29: Sign/Zero Extend/Compute Zero Index ===== */ 01137 i29 = ISA_Pack_Type_Create("i29"); 01138 Operand(0, 0, 0, 6); // qp 01139 Result(0, 6, 7); // r1 01140 Operand(1, 0, 20, 7); // r3 01141 Instruction_Pack_Group(i29, 01142 TOP_zxt1, 0x00080000000ULL, 01143 TOP_zxt2, 0x00088000000ULL, 01144 TOP_zxt4, 0x00090000000ULL, 01145 TOP_sxt1, 0x000a0000000ULL, 01146 TOP_sxt2, 0x000a8000000ULL, 01147 TOP_sxt4, 0x000b0000000ULL, 01148 TOP_czx1_l, 0x000c0000000ULL, 01149 TOP_czx2_l, 0x000c8000000ULL, 01150 TOP_czx1_r, 0x000e0000000ULL, 01151 TOP_czx2_r, 0x000e8000000ULL, 01152 TOP_UNDEFINED); 01153 01154 /* ===== I30: Move to BR (pseudo) ===== */ 01155 i30 = ISA_Pack_Type_Create("i30"); 01156 Operand(0, 0, 0, 6); // qp 01157 Result(0, 6, 3); // b1 01158 Operand(1, 0, 13, 7); // r2 01159 Instruction_Pack_Group(i30, 01160 TOP_mov_t_br, 0x00e00100000ULL, 01161 TOP_UNDEFINED); 01162 01163 /* ===== I31: Test Bit (pseudo) ===== */ 01164 i31 = ISA_Pack_Type_Create("i31"); 01165 Operand(0, 0, 0, 6); // qp 01166 Result(0, 27, 6); // p2 01167 Result(1, 6, 6); // p1 01168 Operand(1, 0, 20, 7); // r3 01169 Operand(2, 0, 14, 6); // pos_6b 01170 Instruction_Pack_Group(i31, 01171 TOP_tbit_nz, 0x0a000000000ULL, 01172 TOP_tbit_nz_unc, 0x0a000001000ULL, 01173 TOP_UNDEFINED); 01174 01175 /* ===== I32: Test NaT (pseudo) ===== */ 01176 i32 = ISA_Pack_Type_Create("i32"); 01177 Operand(0, 0, 0, 6); // qp 01178 Result(0, 27, 6); // p2 01179 Result(1, 6, 6); // p1 01180 Operand(1, 0, 20, 7); // r3 01181 Instruction_Pack_Group(i32, 01182 TOP_tnat_nz, 0x0a000002000ULL, 01183 TOP_tnat_nz_unc, 0x0a000003000ULL, 01184 TOP_UNDEFINED); 01185 01186 /* ===== I33: Shift Left Immediate (pseudo) ===== */ 01187 // NOTE: this packing description is never used (because of the 01188 // 64-count transformation required), it must be lowered to a 01189 // machine inst instead. 01190 i33 = ISA_Pack_Type_Create("i33"); 01191 Operand(0, 0, 0, 6); // qp 01192 Result(0, 6, 7); // r1 01193 Operand(1, 0, 13, 7); // r2 01194 Operand(2, 0, 20, 6); // cpos_6c 01195 Operand(2, 0, 27, 6); // len_6d 01196 Instruction_Pack_Group(i33, 01197 TOP_shl_i, 0x0a600000000ULL, 01198 TOP_UNDEFINED); 01199 01200 /* ===== I34: Shift Right Immediate (pseudo) ===== */ 01201 // NOTE: this packing description is never used (because of the 01202 // 64-count transformation required), it must be lowered to a 01203 // machine inst instead. 01204 i34 = ISA_Pack_Type_Create("i34"); 01205 Operand(0, 0, 0, 6); // qp 01206 Result(0, 6, 7); // r1 01207 Operand(1, 0, 20, 7); // r3 01208 Operand(2, 0, 14, 6); // pos_6b 01209 Operand(2, 0, 27, 6); // len_6d 01210 Instruction_Pack_Group(i34, 01211 TOP_shr_i_u, 0x0a400000000ULL, 01212 TOP_shr_i, 0x0a400002000ULL, 01213 TOP_UNDEFINED); 01214 01215 /* ===== M1a: Integer Load ===== */ 01216 m1a = ISA_Pack_Type_Create("m1a"); 01217 Operand(0, 0, 0, 6); // qp 01218 Operand(1, 0, 32, 4); // ldtype 01219 Operand(2, 0, 28, 2); // ldhint 01220 Result(0, 6, 7); // r1 01221 Operand(3, 0, 20, 7); // r3 01222 Instruction_Pack_Group(m1a, 01223 TOP_ld1, 0x08000000000ULL, 01224 TOP_ld2, 0x08040000000ULL, 01225 TOP_ld4, 0x08080000000ULL, 01226 TOP_ld8, 0x080c0000000ULL, 01227 TOP_UNDEFINED); 01228 01229 /* ===== M1b: Integer Load ===== */ 01230 m1b = ISA_Pack_Type_Create("m1b"); 01231 Operand(0, 0, 0, 6); // qp 01232 Operand(1, 0, 28, 2); // ldhint 01233 Result(0, 6, 7); // r1 01234 Operand(2, 0, 20, 7); // r3 01235 Instruction_Pack_Group(m1b, 01236 TOP_ld8_fill, 0x086c0000000ULL, 01237 TOP_UNDEFINED); 01238 01239 /* ===== M2a: Integer Load -- Increment by Register ===== */ 01240 m2a = ISA_Pack_Type_Create("m2a"); 01241 Operand(0, 0, 0, 6); // qp 01242 Operand(1, 0, 32, 4); // ldtype 01243 Operand(2, 0, 28, 2); // ldhint 01244 Result(0, 6, 7); // r1 01245 Operand(3, 0, 20, 7); // r3 01246 Operand(4, 0, 13, 7); // r2 01247 Instruction_Pack_Group(m2a, 01248 TOP_ld1_r, 0x09000000000ULL, 01249 TOP_ld2_r, 0x09040000000ULL, 01250 TOP_ld4_r, 0x09080000000ULL, 01251 TOP_ld8_r, 0x090c0000000ULL, 01252 TOP_UNDEFINED); 01253 01254 /* ===== M2b: Integer Load -- Increment by Register ===== */ 01255 m2b = ISA_Pack_Type_Create("m2b"); 01256 Operand(0, 0, 0, 6); // qp 01257 Operand(1, 0, 28, 2); // ldhint 01258 Result(0, 6, 7); // r1 01259 Operand(2, 0, 20, 7); // r3 01260 Operand(3, 0, 13, 7); // r2 01261 Instruction_Pack_Group(m2b, 01262 TOP_ld8_r_fill, 0x096c0000000ULL, 01263 TOP_UNDEFINED); 01264 01265 /* ===== M3a: Integer Load -- Increment by Immediate ===== */ 01266 m3a = ISA_Pack_Type_Create("m3a"); 01267 Operand(0, 0, 0, 6); // qp 01268 Operand(1, 0, 32, 4); // ldtype 01269 Operand(2, 0, 28, 2); // ldhint 01270 Result(0, 6, 7); // r1 01271 Operand(3, 0, 20, 7); // r3 01272 Operand(4, 0, 13, 7); // imm_7b 01273 Operand(4, 7, 27, 1); // i 01274 Operand(4, 8, 36, 1); // s 01275 Instruction_Pack_Group(m3a, 01276 TOP_ld1_i, 0x0a000000000ULL, 01277 TOP_ld2_i, 0x0a040000000ULL, 01278 TOP_ld4_i, 0x0a080000000ULL, 01279 TOP_ld8_i, 0x0a0c0000000ULL, 01280 TOP_UNDEFINED); 01281 01282 /* ===== M3b: Integer Load -- Increment by Immediate ===== */ 01283 m3b = ISA_Pack_Type_Create("m3b"); 01284 Operand(0, 0, 0, 6); // qp 01285 Operand(1, 0, 28, 2); // ldhint 01286 Result(0, 6, 7); // r1 01287 Operand(2, 0, 20, 7); // r3 01288 Operand(3, 0, 13, 7); // imm_7b 01289 Operand(3, 7, 27, 1); // i 01290 Operand(3, 8, 36, 1); // s 01291 Instruction_Pack_Group(m3b, 01292 TOP_ld8_i_fill, 0x0a6c0000000ULL, 01293 TOP_UNDEFINED); 01294 01295 /* ===== M4a: Integer Store ===== */ 01296 m4a = ISA_Pack_Type_Create("m4a"); 01297 Operand(0, 0, 0, 6); // qp 01298 Operand(1, 0, 32, 1); // sttype 01299 Operand(2, 0, 28, 2); // sthint 01300 Operand(3, 0, 20, 7); // r3 01301 Operand(4, 0, 13, 7); // r2 01302 Instruction_Pack_Group(m4a, 01303 TOP_st1, 0x08c00000000ULL, 01304 TOP_st2, 0x08c40000000ULL, 01305 TOP_st4, 0x08c80000000ULL, 01306 TOP_st8, 0x08cc0000000ULL, 01307 TOP_UNDEFINED); 01308 01309 /* ===== M4b: Integer Store ===== */ 01310 m4b = ISA_Pack_Type_Create("m4b"); 01311 Operand(0, 0, 0, 6); // qp 01312 Operand(1, 0, 28, 2); // sthint 01313 Operand(2, 0, 20, 7); // r3 01314 Operand(3, 0, 13, 7); // r2 01315 Instruction_Pack_Group(m4b, 01316 TOP_st8_spill, 0x08ec0000000ULL, 01317 TOP_UNDEFINED); 01318 01319 /* ===== M5a: Integer Store -- Increment by Immediate ===== */ 01320 m5a = ISA_Pack_Type_Create("m5a"); 01321 Operand(0, 0, 0, 6); // qp 01322 Operand(1, 0, 32, 1); // sttype 01323 Operand(2, 0, 28, 2); // sthint 01324 Operand(3, 0, 20, 7); // r3 01325 Operand(4, 0, 13, 7); // r2 01326 Operand(5, 0, 6, 7); // imm_7a 01327 Operand(5, 7, 27, 1); // i 01328 Operand(5, 8, 36, 1); // s 01329 Instruction_Pack_Group(m5a, 01330 TOP_st1_i, 0x0ac00000000ULL, 01331 TOP_st2_i, 0x0ac40000000ULL, 01332 TOP_st4_i, 0x0ac80000000ULL, 01333 TOP_st8_i, 0x0acc0000000ULL, 01334 TOP_UNDEFINED); 01335 01336 /* ===== M5b: Integer Store -- Increment by Immediate ===== */ 01337 m5b = ISA_Pack_Type_Create("m5b"); 01338 Operand(0, 0, 0, 6); // qp 01339 Operand(1, 0, 28, 2); // sthint 01340 Operand(2, 0, 20, 7); // r3 01341 Operand(3, 0, 13, 7); // r2 01342 Operand(4, 0, 6, 7); // imm_7a 01343 Operand(4, 7, 27, 1); // i 01344 Operand(4, 8, 36, 1); // s 01345 Instruction_Pack_Group(m5b, 01346 TOP_st8_i_spill, 0x0aec0000000ULL, 01347 TOP_UNDEFINED); 01348 01349 /* ===== M6a: Floating-point Load ===== */ 01350 m6a = ISA_Pack_Type_Create("m6a"); 01351 Operand(0, 0, 0, 6); // qp 01352 Operand(1, 0, 32, 4); // fldtype 01353 Operand(2, 0, 28, 2); // ldhint 01354 Result(0, 6, 7); // f1 01355 Operand(3, 0, 20, 7); // r3 01356 Instruction_Pack_Group(m6a, 01357 TOP_ldfs, 0x0c080000000ULL, 01358 TOP_ldfd, 0x0c0c0000000ULL, 01359 TOP_ldf8, 0x0c040000000ULL, 01360 TOP_ldfe, 0x0c000000000ULL, 01361 TOP_UNDEFINED); 01362 01363 /* ===== M6b: Floating-point Load ===== */ 01364 m6b = ISA_Pack_Type_Create("m6b"); 01365 Operand(0, 0, 0, 6); // qp 01366 Operand(1, 0, 28, 2); // ldhint 01367 Result(0, 6, 7); // f1 01368 Operand(2, 0, 20, 7); // r3 01369 Instruction_Pack_Group(m6b, 01370 TOP_ldf_fill, 0x0c6c0000000ULL, 01371 TOP_UNDEFINED); 01372 01373 /* ===== M7a: Floating-point Load -- Increment by Register ===== */ 01374 m7a = ISA_Pack_Type_Create("m7a"); 01375 Operand(0, 0, 0, 6); // qp 01376 Operand(1, 0, 32, 4); // fldtype 01377 Operand(2, 0, 28, 2); // ldhint 01378 Result(0, 6, 7); // f1 01379 Operand(3, 0, 20, 7); // r3 01380 Operand(4, 0, 13, 7); // r2 01381 Instruction_Pack_Group(m7a, 01382 TOP_ldfs_r, 0x0d080000000ULL, 01383 TOP_ldfd_r, 0x0d0c0000000ULL, 01384 TOP_ldf8_r, 0x0d040000000ULL, 01385 TOP_ldfe_r, 0x0d000000000ULL, 01386 TOP_UNDEFINED); 01387 01388 /* ===== M7b: Floating-point Load -- Increment by Register ===== */ 01389 m7b = ISA_Pack_Type_Create("m7b"); 01390 Operand(0, 0, 0, 6); // qp 01391 Operand(1, 0, 28, 2); // ldhint 01392 Result(0, 6, 7); // f1 01393 Operand(2, 0, 20, 7); // r3 01394 Operand(3, 0, 13, 7); // r2 01395 Instruction_Pack_Group(m7b, 01396 TOP_ldf_r_fill, 0x0d6c0000000ULL, 01397 TOP_UNDEFINED); 01398 01399 /* ===== M8a: Floating-point Load -- Increment by Immediate ===== */ 01400 m8a = ISA_Pack_Type_Create("m8a"); 01401 Operand(0, 0, 0, 6); // qp 01402 Operand(1, 0, 32, 4); // fldtype 01403 Operand(2, 0, 28, 2); // ldhint 01404 Result(0, 6, 7); // f1 01405 Operand(3, 0, 20, 7); // r3 01406 Operand(4, 0, 13, 7); // imm_7a 01407 Operand(4, 7, 27, 1); // i 01408 Operand(4, 8, 36, 1); // s 01409 Instruction_Pack_Group(m8a, 01410 TOP_ldfs_i, 0x0e080000000ULL, 01411 TOP_ldfd_i, 0x0e0c0000000ULL, 01412 TOP_ldf8_i, 0x0e040000000ULL, 01413 TOP_ldfe_i, 0x0e000000000ULL, 01414 TOP_UNDEFINED); 01415 01416 /* ===== M8b: Floating-point Load -- Increment by Immediate ===== */ 01417 m8b = ISA_Pack_Type_Create("m8b"); 01418 Operand(0, 0, 0, 6); // qp 01419 Operand(1, 0, 28, 2); // ldhint 01420 Result(0, 6, 7); // f1 01421 Operand(2, 0, 20, 7); // r3 01422 Operand(3, 0, 13, 7); // imm_7a 01423 Operand(3, 7, 27, 1); // i 01424 Operand(3, 8, 36, 1); // s 01425 Instruction_Pack_Group(m8b, 01426 TOP_ldf_i_fill, 0x0e6c0000000ULL, 01427 TOP_UNDEFINED); 01428 01429 /* ===== M9: Floating-point Store ===== */ 01430 m9 = ISA_Pack_Type_Create("m9"); 01431 Operand(0, 0, 0, 6); // qp 01432 Operand(1, 0, 28, 2); // sthint 01433 Operand(2, 0, 20, 7); // r3 01434 Operand(3, 0, 13, 7); // f2 01435 Instruction_Pack_Group(m9, 01436 TOP_stfs, 0x0cc80000000ULL, 01437 TOP_stfd, 0x0ccc0000000ULL, 01438 TOP_stf8, 0x0cc40000000ULL, 01439 TOP_stfe, 0x0cc00000000ULL, 01440 TOP_stf_spill, 0x0cec0000000ULL, 01441 TOP_UNDEFINED); 01442 01443 /* ===== M10: Floating-point Store -- Increment by Immediate ===== */ 01444 m10 = ISA_Pack_Type_Create("m10"); 01445 Operand(0, 0, 0, 6); // qp 01446 Operand(1, 0, 28, 2); // sthint 01447 Operand(2, 0, 20, 7); // r3 01448 Operand(3, 0, 13, 7); // f2 01449 Operand(4, 0, 6, 7); // imm_7a 01450 Operand(4, 7, 27, 1); // i 01451 Operand(4, 8, 36, 1); // s 01452 Instruction_Pack_Group(m10, 01453 TOP_stfs_i, 0x0ec80000000ULL, 01454 TOP_stfd_i, 0x0ecc0000000ULL, 01455 TOP_stf8_i, 0x0ec40000000ULL, 01456 TOP_stfe_i, 0x0ec00000000ULL, 01457 TOP_stf_i_spill, 0x0eec0000000ULL, 01458 TOP_UNDEFINED); 01459 01460 /* ===== M11: Floating-point Load Pair ===== */ 01461 m11 = ISA_Pack_Type_Create("m11"); 01462 Operand(0, 0, 0, 6); // qp 01463 Operand(1, 0, 32, 4); // fldtype 01464 Operand(2, 0, 28, 2); // ldhint 01465 Result(0, 6, 7); // f1 01466 Result(1, 13, 7); // f2 01467 Operand(3, 0, 20, 7); // r3 01468 Instruction_Pack_Group(m11, 01469 TOP_ldfps, 0x0c088000000ULL, 01470 TOP_ldfpd, 0x0c0c8000000ULL, 01471 TOP_ldfp8, 0x0c048000000ULL, 01472 TOP_UNDEFINED); 01473 01474 /* ===== M12: Floating-point Load Pair -- Increment by Immediate ===== */ 01475 m12 = ISA_Pack_Type_Create("m12"); 01476 Operand(0, 0, 0, 6); // qp 01477 Operand(1, 0, 32, 4); // fldtype 01478 Operand(2, 0, 28, 2); // ldhint 01479 Result(0, 6, 7); // f1 01480 Result(1, 13, 7); // f2 01481 Operand(3, 0, 20, 7); // r3 01482 Instruction_Pack_Group(m12, 01483 TOP_ldfps_i, 0x0d088000000ULL, 01484 TOP_ldfpd_i, 0x0d0c8000000ULL, 01485 TOP_ldfp8_i, 0x0d048000000ULL, 01486 TOP_UNDEFINED); 01487 01488 /* ===== M13: Line Prefetch ===== */ 01489 m13 = ISA_Pack_Type_Create("m13"); 01490 Operand(0, 0, 0, 6); // qp 01491 Operand(1, 0, 28, 2); // lfhint 01492 Operand(2, 0, 20, 7); // r3 01493 Instruction_Pack_Group(m13, 01494 TOP_lfetch, 0x0cb00000000ULL, 01495 TOP_lfetch_excl, 0x0cb40000000ULL, 01496 TOP_lfetch_fault, 0x0cb80000000ULL, 01497 TOP_lfetch_fault_excl, 0x0cbc0000000ULL, 01498 TOP_UNDEFINED); 01499 01500 /* ===== M14: Line Prefetch -- Increment by Register ===== */ 01501 m14 = ISA_Pack_Type_Create("m14"); 01502 Operand(0, 0, 0, 6); // qp 01503 Operand(1, 0, 28, 2); // lfhint 01504 Operand(2, 0, 20, 7); // r3 01505 Operand(3, 0, 13, 7); // r2 01506 Instruction_Pack_Group(m14, 01507 TOP_lfetch_r, 0x0db00000000ULL, 01508 TOP_lfetch_r_excl, 0x0db40000000ULL, 01509 TOP_lfetch_r_fault, 0x0db80000000ULL, 01510 TOP_lfetch_r_fault_excl,0x0dbc0000000ULL, 01511 TOP_UNDEFINED); 01512 01513 /* ===== M15: Line Prefetch -- Increment by Immediate ===== */ 01514 m15 = ISA_Pack_Type_Create("m15"); 01515 Operand(0, 0, 0, 6); // qp 01516 Operand(1, 0, 28, 2); // lfhint 01517 Operand(2, 0, 20, 7); // r3 01518 Operand(3, 0, 13, 7); // imm_7b 01519 Operand(3, 7, 27, 1); // i 01520 Operand(3, 8, 36, 1); // s 01521 Instruction_Pack_Group(m15, 01522 TOP_lfetch_i, 0x0eb00000000ULL, 01523 TOP_lfetch_i_excl, 0x0eb40000000ULL, 01524 TOP_lfetch_i_fault, 0x0eb80000000ULL, 01525 TOP_lfetch_i_fault_excl,0x0ebc0000000ULL, 01526 TOP_UNDEFINED); 01527 01528 /* ===== M16a: Exchange/Compare and Exchange ===== */ 01529 m16a = ISA_Pack_Type_Create("m16a"); 01530 Operand(0, 0, 0, 6); // qp 01531 Operand(1, 0, 32, 1); // sem 01532 Operand(2, 0, 28, 2); // ldhint 01533 Result(0, 6, 7); // r1 01534 Operand(3, 0, 20, 7); // r3 01535 Operand(4, 0, 13, 7); // r2 01536 Instruction_Pack_Group(m16a, 01537 TOP_cmpxchg1, 0x08008000000ULL, 01538 TOP_cmpxchg2, 0x08048000000ULL, 01539 TOP_cmpxchg4, 0x08088000000ULL, 01540 TOP_cmpxchg8, 0x080c8000000ULL, 01541 TOP_UNDEFINED); 01542 01543 /* ===== M16b: Exchange/Compare and Exchange ===== */ 01544 m16b = ISA_Pack_Type_Create("m16b"); 01545 Operand(0, 0, 0, 6); // qp 01546 Operand(1, 0, 28, 2); // ldhint 01547 Result(0, 6, 7); // r1 01548 Operand(2, 0, 20, 7); // r3 01549 Operand(3, 0, 13, 7); // r2 01550 Instruction_Pack_Group(m16b, 01551 TOP_xchg1, 0x08208000000ULL, 01552 TOP_xchg2, 0x08248000000ULL, 01553 TOP_xchg4, 0x08288000000ULL, 01554 TOP_xchg8, 0x082c8000000ULL, 01555 TOP_UNDEFINED); 01556 01557 /* ===== M17: Fetch and Add -- Immediate ===== */ 01558 m17 = ISA_Pack_Type_Create("m17"); 01559 Operand(0, 0, 0, 6); // qp 01560 Operand(1, 0, 32, 1); // sem 01561 Operand(2, 0, 28, 2); // ldhint 01562 Result(0, 6, 7); // r1 01563 Operand(3, 0, 20, 7); // r3 01564 Adjust_Operand(4, pack_m17, unpack_m17); 01565 Operand(4, 0, 13, 3); // i_2b/s 01566 Instruction_Pack_Group(m17, 01567 TOP_fetchadd4, 0x08488000000ULL, 01568 TOP_fetchadd8, 0x084c8000000ULL, 01569 TOP_UNDEFINED); 01570 01571 /* ===== M18: Set FR ===== */ 01572 m18 = ISA_Pack_Type_Create("m18"); 01573 Operand(0, 0, 0, 6); // qp 01574 Result(0, 6, 7); // f1 01575 Operand(1, 0, 13, 7); // r2 01576 Instruction_Pack_Group(m18, 01577 TOP_setf_sig, 0x0c708000000ULL, 01578 TOP_setf_exp, 0x0c748000000ULL, 01579 TOP_setf_s, 0x0c788000000ULL, 01580 TOP_setf_d, 0x0c7c8000000ULL, 01581 TOP_UNDEFINED); 01582 01583 /* ===== M19: Get FR ===== */ 01584 m19 = ISA_Pack_Type_Create("m19"); 01585 Operand(0, 0, 0, 6); // qp 01586 Result(0, 6, 7); // r1 01587 Operand(1, 0, 13, 7); // f2 01588 Instruction_Pack_Group(m19, 01589 TOP_getf_sig, 0x08708000000ULL, 01590 TOP_getf_exp, 0x08748000000ULL, 01591 TOP_getf_s, 0x08788000000ULL, 01592 TOP_getf_d, 0x087c8000000ULL, 01593 TOP_UNDEFINED); 01594 01595 /* ===== M20: Integer Speculation Check ===== */ 01596 m20 = ISA_Pack_Type_Create("m20"); 01597 Operand(0, 0, 0, 6); // qp 01598 Operand(1, 0, 13, 7); // r2 01599 // Adjust_Operand(2, shr4, shl4); // imm_21 = target_25 >> 4 01600 Operand(2, 4, 6, 7); // imm_7a 01601 Operand(2, 11, 20, 13); // imm_13c 01602 Operand(2, 24, 36, 1); // s 01603 Instruction_Pack_Group(m20, 01604 TOP_chk_s_m, 0x02200000000ULL, 01605 TOP_UNDEFINED); 01606 01607 /* ===== M21: Floating-point Speculation Check ===== */ 01608 m21 = ISA_Pack_Type_Create("m21"); 01609 Operand(0, 0, 0, 6); // qp 01610 Operand(1, 0, 13, 7); // f2 01611 // Adjust_Operand(2, shr4, shl4); // imm_21 = target_25 >> 4 01612 Operand(2, 4, 6, 7); // imm_7a 01613 Operand(2, 11, 20, 13); // imm_13c 01614 Operand(2, 24, 36, 1); // s 01615 Instruction_Pack_Group(m21, 01616 TOP_chk_f_s, 0x02600000000ULL, 01617 TOP_UNDEFINED); 01618 01619 /* ===== M22: Integer Advanced Load Check ===== */ 01620 m22 = ISA_Pack_Type_Create("m22"); 01621 Operand(0, 0, 0, 6); // qp 01622 Operand(1, 0, 33, 1); // aclr 01623 Operand(2, 0, 6, 7); // r1 01624 // Adjust_Operand(3, shr4, shl4); // imm_21 = target_25 >> 4 01625 Operand(3, 4, 13, 20); // imm_20b 01626 Operand(3, 24, 36, 1); // s 01627 Instruction_Pack_Group(m22, 01628 TOP_chk_a, 0x00800000000ULL, 01629 TOP_UNDEFINED); 01630 01631 /* ===== M23: Floating-point Advanced Load Check ===== */ 01632 m23 = ISA_Pack_Type_Create("m23"); 01633 Operand(0, 0, 0, 6); // qp 01634 Operand(1, 0, 33, 1); // aclr 01635 Operand(2, 0, 6, 7); // f1 01636 // Adjust_Operand(3, shr4, shl4); // imm_21 = target_25 >> 4 01637 Operand(3, 4, 13, 20); // imm_20b 01638 Operand(3, 24, 36, 1); // s 01639 Instruction_Pack_Group(m23, 01640 TOP_chk_f_a, 0x00c00000000ULL, 01641 TOP_UNDEFINED); 01642 01643 /* ===== M24: Sync/Fence/Serialize/ALAT Control ===== */ 01644 m24 = ISA_Pack_Type_Create("m24"); 01645 Operand(0, 0, 0, 6); // qp 01646 Instruction_Pack_Group(m24, 01647 TOP_invala, 0x00080000000ULL, 01648 TOP_fwb, 0x00100000000ULL, 01649 TOP_mf, 0x00110000000ULL, 01650 TOP_mf_a, 0x00118000000ULL, 01651 TOP_srlz_d, 0x00180000000ULL, 01652 TOP_srlz_i, 0x00188000000ULL, 01653 TOP_sync_i, 0x00198000000ULL, 01654 TOP_UNDEFINED); 01655 01656 /* ===== M25: RSE Control ===== */ 01657 m25 = ISA_Pack_Type_Create("m25"); 01658 Instruction_Pack_Group(m25, 01659 TOP_flushrs, 0x00060000000ULL, 01660 TOP_loadrs, 0x00050000000ULL, 01661 TOP_UNDEFINED); 01662 01663 /* ===== M26: Integer ALAT Entry Invalidate ===== */ 01664 m26 = ISA_Pack_Type_Create("m26"); 01665 Operand(0, 0, 0, 6); // qp 01666 Operand(1, 0, 6, 7); // r1 01667 Instruction_Pack_Group(m26, 01668 TOP_invala_e, 0x00090000000ULL, 01669 TOP_UNDEFINED); 01670 01671 /* ===== M27: Floating-point ALAT Entry Invalidate ===== */ 01672 m27 = ISA_Pack_Type_Create("m27"); 01673 Operand(0, 0, 0, 6); // qp 01674 Operand(1, 0, 6, 7); // f1 01675 Instruction_Pack_Group(m27, 01676 TOP_invala_f_e, 0x00098000000ULL, 01677 TOP_UNDEFINED); 01678 01679 /* ===== M28: Flush Cache/Purge Translation Cache Entry ===== */ 01680 m28 = ISA_Pack_Type_Create("m28"); 01681 Operand(0, 0, 0, 6); // qp 01682 Operand(1, 0, 20, 7); // r3 01683 Instruction_Pack_Group(m28, 01684 TOP_fc, 0x02180000000ULL, 01685 TOP_ptc_e, 0x021a0000000ULL, 01686 TOP_UNDEFINED); 01687 01688 /* ===== M29: Move to AR -- Register ===== */ 01689 m29 = ISA_Pack_Type_Create("m29"); 01690 Operand(0, 0, 0, 6); // qp 01691 Result(0, 20, 7); // ar3 01692 Operand(1, 0, 13, 7); // r2 01693 Instruction_Pack_Group(m29, 01694 TOP_mov_t_ar_r_m, 0x02150000000ULL, 01695 TOP_UNDEFINED); 01696 01697 /* ===== M30: Move to AR -- Immediate_8 ===== */ 01698 m30 = ISA_Pack_Type_Create("m30"); 01699 Operand(0, 0, 0, 6); // qp 01700 Result(0, 20, 7); // ar3 01701 Operand(1, 0, 13, 7); // imm_7b 01702 Operand(1, 7, 36, 1); // s 01703 Instruction_Pack_Group(m30, 01704 TOP_mov_t_ar_i_m, 0x00140000000ULL, 01705 TOP_UNDEFINED); 01706 01707 /* ===== M31: Move from AR ===== */ 01708 m31 = ISA_Pack_Type_Create("m31"); 01709 Operand(0, 0, 0, 6); // qp 01710 Result(0, 6, 7); // r1 01711 Operand(1, 0, 20, 7); // ar3 01712 Instruction_Pack_Group(m31, 01713 TOP_mov_f_ar_m, 0x02110000000ULL, 01714 TOP_UNDEFINED); 01715 01716 /* ===== M32: Move to CR ===== */ 01717 m32 = ISA_Pack_Type_Create("m32"); 01718 Operand(0, 0, 0, 6); // qp 01719 Result(0, 20, 7); // cr3 01720 Operand(1, 0, 13, 7); // r2 01721 Instruction_Pack_Group(m32, 01722 TOP_mov_t_cr, 0x02160000000ULL, 01723 TOP_UNDEFINED); 01724 01725 /* ===== M33: Move from CR ===== */ 01726 m33 = ISA_Pack_Type_Create("m33"); 01727 Operand(0, 0, 0, 6); // qp 01728 Result(0, 6, 7); // r1 01729 Operand(1, 0, 20, 7); // cr3 01730 Instruction_Pack_Group(m33, 01731 TOP_mov_f_cr, 0x02120000000ULL, 01732 TOP_UNDEFINED); 01733 01734 /* ===== M34: Allocate Register Stack Frame ===== */ 01735 m34 = ISA_Pack_Type_Create("m34"); 01736 Result(0, 6, 7); // r1 01737 Operand(0, 0, 13, 7); // sof 01738 Operand(1, 0, 20, 7); // sol 01739 Operand(2, 3, 27, 4); // sor >> 3 01740 Instruction_Pack_Group(m34, 01741 TOP_alloc_3, 0x02c00000000ULL, 01742 TOP_UNDEFINED); 01743 01744 /* ===== M35: Move to PSR ===== */ 01745 m35 = ISA_Pack_Type_Create("m35"); 01746 Operand(0, 0, 0, 6); // qp 01747 Operand(1, 0, 13, 7); // r2 01748 Instruction_Pack_Group(m35, 01749 TOP_mov_t_psr, 0x02168000000ULL, 01750 TOP_mov_t_psrum, 0x02148000000ULL, 01751 TOP_UNDEFINED); 01752 01753 /* ===== M36: Move from PSR ===== */ 01754 m36 = ISA_Pack_Type_Create("m36"); 01755 Operand(0, 0, 0, 6); // qp 01756 Result(0, 6, 7); // r1 01757 Instruction_Pack_Group(m36, 01758 TOP_mov_f_psr, 0x02128000000ULL, 01759 TOP_mov_f_psrum, 0x02108000000ULL, 01760 TOP_UNDEFINED); 01761 01762 /* ===== M37: Break/Nop ===== */ 01763 m37 = ISA_Pack_Type_Create("m37"); 01764 Operand(0, 0, 0, 6); // qp 01765 Operand(1, 0, 6, 20); // imm_20a 01766 Operand(1, 20, 36, 1); // i 01767 Instruction_Pack_Group(m37, 01768 TOP_break_m, 0x00000000000ULL, 01769 TOP_nop_m, 0x00008000000ULL, 01770 TOP_UNDEFINED); 01771 01772 /* ===== M38: Probe -- Register ===== */ 01773 m38 = ISA_Pack_Type_Create("m38"); 01774 Operand(0, 0, 0, 6); // qp 01775 Result(0, 6, 7); // r1 01776 Operand(1, 0, 20, 7); // r3 01777 Operand(2, 0, 13, 7); // r2 01778 Instruction_Pack_Group(m38, 01779 TOP_probe_r, 0x021c0000000ULL, 01780 TOP_probe_w, 0x021c8000000ULL, 01781 TOP_UNDEFINED); 01782 01783 /* ===== M39: Probe -- Immediate_2 ===== */ 01784 m39 = ISA_Pack_Type_Create("m39"); 01785 Operand(0, 0, 0, 6); // qp 01786 Result(0, 6, 7); // r1 01787 Operand(1, 0, 20, 7); // r3 01788 Operand(2, 0, 13, 2); // i_2b 01789 Instruction_Pack_Group(m39, 01790 TOP_probe_i_r, 0x020c0000000ULL, 01791 TOP_probe_i_w, 0x020c8000000ULL, 01792 TOP_UNDEFINED); 01793 01794 /* ===== M40: Probe Fault ===== */ 01795 m40 = ISA_Pack_Type_Create("m40"); 01796 Operand(0, 0, 0, 6); // qp 01797 Operand(1, 0, 20, 7); // r3 01798 Operand(2, 0, 13, 2); // i_2b 01799 Instruction_Pack_Group(m40, 01800 TOP_probe_r_fault, 0x02190000000ULL, 01801 TOP_probe_w_fault, 0x02198000000ULL, 01802 TOP_probe_rw_fault, 0x02188000000ULL, 01803 TOP_UNDEFINED); 01804 01805 /* ===== M41: Translation Cache Insert ===== */ 01806 m41 = ISA_Pack_Type_Create("m41"); 01807 Operand(0, 0, 0, 6); // qp 01808 Operand(1, 0, 13, 7); // r2 01809 Instruction_Pack_Group(m41, 01810 TOP_itc_d, 0x02170000000ULL, 01811 TOP_itc_i, 0x02178000000ULL, 01812 TOP_UNDEFINED); 01813 01814 /* ===== M42: Move to Indirect Register/Translation Register Insert ===== */ 01815 m42 = ISA_Pack_Type_Create("m42"); 01816 Operand(0, 0, 0, 6); // qp 01817 Operand(1, 0, 20, 7); // r3 01818 Operand(2, 0, 13, 7); // r2 01819 Instruction_Pack_Group(m42, 01820 TOP_mov_t_rr, 0x02000000000ULL, 01821 TOP_mov_t_dbr, 0x02008000000ULL, 01822 TOP_mov_t_ibr, 0x02010000000ULL, 01823 TOP_mov_t_pkr, 0x02018000000ULL, 01824 TOP_mov_t_pmc, 0x02020000000ULL, 01825 TOP_mov_t_pmd, 0x02028000000ULL, 01826 TOP_mov_t_msr, 0x02030000000ULL, 01827 TOP_itr_d, 0x02070000000ULL, 01828 TOP_itr_i, 0x02078000000ULL, 01829 TOP_UNDEFINED); 01830 01831 /* ===== M43: Move from Indirect Register ===== */ 01832 m43 = ISA_Pack_Type_Create("m43"); 01833 Operand(0, 0, 0, 6); // qp 01834 Result(0, 6, 7); // r1 01835 Operand(1, 0, 20, 7); // r3 01836 Instruction_Pack_Group(m43, 01837 TOP_mov_f_rr, 0x02080000000ULL, 01838 TOP_mov_f_dbr, 0x02088000000ULL, 01839 TOP_mov_f_ibr, 0x02090000000ULL, 01840 TOP_mov_f_pkr, 0x02098000000ULL, 01841 TOP_mov_f_pmc, 0x020a0000000ULL, 01842 TOP_mov_f_pmd, 0x020a8000000ULL, 01843 TOP_mov_f_msr, 0x020b0000000ULL, 01844 TOP_mov_f_cpuid, 0x020b8000000ULL, 01845 TOP_UNDEFINED); 01846 01847 /* ===== M44: Set/Reset User/System Mask ===== */ 01848 m44 = ISA_Pack_Type_Create("m44"); 01849 Operand(0, 0, 0, 6); // qp 01850 Operand(1, 0, 6, 21); // imm_21a 01851 Operand(1, 21, 31, 2); // i_2d 01852 Operand(1, 23, 36, 1); // i 01853 Instruction_Pack_Group(m44, 01854 TOP_sum, 0x00020000000ULL, 01855 TOP_rum, 0x00028000000ULL, 01856 TOP_ssm, 0x00030000000ULL, 01857 TOP_rsm, 0x00038000000ULL, 01858 TOP_UNDEFINED); 01859 01860 /* ===== M45: Translation Purge ===== */ 01861 m45 = ISA_Pack_Type_Create("m45"); 01862 Operand(0, 0, 0, 6); // qp 01863 Operand(1, 0, 20, 7); // r3 01864 Operand(2, 0, 13, 7); // r2 01865 Instruction_Pack_Group(m45, 01866 TOP_ptc_l, 0x02048000000ULL, 01867 TOP_ptc_g, 0x02050000000ULL, 01868 TOP_ptc_ga, 0x02058000000ULL, 01869 TOP_ptr_d, 0x02060000000ULL, 01870 TOP_ptr_i, 0x02068000000ULL, 01871 TOP_UNDEFINED); 01872 01873 /* ===== M46: Translation Access ===== */ 01874 m46 = ISA_Pack_Type_Create("m46"); 01875 Operand(0, 0, 0, 6); // qp 01876 Result(0, 6, 7); // r1 01877 Operand(1, 0, 20, 7); // r3 01878 Instruction_Pack_Group(m46, 01879 TOP_thash, 0x020d0000000ULL, 01880 TOP_ttag, 0x020d8000000ULL, 01881 TOP_tpa, 0x020f0000000ULL, 01882 TOP_tak, 0x020f8000000ULL, 01883 TOP_UNDEFINED); 01884 01885 /* ===== M47: Allocate Register Stack Frame (pseudo) ===== */ 01886 // NOTE: this packing description is never used (because of the 01887 // operand transformations required), it must be lowered to a 01888 // machine inst instead. 01889 m47 = ISA_Pack_Type_Create("m47"); 01890 Result(0, 6, 7); // r1 01891 Operand(0, 0, 13, 7); // i 01892 Operand(1, 0, 20, 7); // l 01893 Operand(2, 0, 0, 0); // o 01894 Operand(3, 0, 27, 4); // r 01895 Instruction_Pack_Group(m47, 01896 TOP_alloc, 0x02c00000000ULL, 01897 TOP_UNDEFINED); 01898 01899 /* ===== B1: IP-Relative Branch ===== */ 01900 b1 = ISA_Pack_Type_Create("b1"); 01901 Operand(0, 0, 0, 6); // qp 01902 Operand(1, 0, 33, 2); // bwh 01903 Operand(2, 0, 12, 1); // ph 01904 Operand(3, 0, 35, 1); // dh 01905 // Adjust_Operand(4, shr4, shl4); // imm_21 = target_25 >> 4 01906 Operand(4, 4, 13, 20); // imm_20b 01907 Operand(4, 24, 36, 1); // s 01908 Instruction_Pack_Group(b1, 01909 TOP_br_cond, 0x08000000000ULL, 01910 TOP_br_wexit, 0x08000000080ULL, 01911 TOP_br_wtop, 0x080000000c0ULL, 01912 TOP_UNDEFINED); 01913 01914 /* ===== B2: IP-Relative Counted Branch ===== */ 01915 b2 = ISA_Pack_Type_Create("b2"); 01916 Operand(0, 0, 33, 2); // bwh 01917 Operand(1, 0, 12, 1); // ph 01918 Operand(2, 0, 35, 1); // dh 01919 // Adjust_Operand(3, shr4, shl4); // imm_21 = target_25 >> 4 01920 Operand(3, 4, 13, 20); // imm_20b 01921 Operand(3, 24, 36, 1); // s 01922 Instruction_Pack_Group(b2, 01923 TOP_br_cloop, 0x08000000140ULL, 01924 TOP_br_cexit, 0x08000000180ULL, 01925 TOP_br_ctop, 0x080000001c0ULL, 01926 TOP_UNDEFINED); 01927 01928 /* ===== B3: IP-Relative Call ===== */ 01929 b3 = ISA_Pack_Type_Create("b3"); 01930 Operand(0, 0, 0, 6); // qp 01931 Operand(1, 0, 33, 2); // bwh 01932 Operand(2, 0, 12, 1); // ph 01933 Operand(3, 0, 35, 1); // dh 01934 Result(0, 6, 3); // b1 01935 // Adjust_Operand(4, shr4, shl4); // imm_21 = target_25 >> 4 01936 Operand(4, 4, 13, 20); // imm_20b 01937 Operand(4, 24, 36, 1); // s 01938 Instruction_Pack_Group(b3, 01939 TOP_br_call, 0x0a000000000ULL, 01940 TOP_UNDEFINED); 01941 01942 /* ===== B4: Indirect Branch ===== */ 01943 b4 = ISA_Pack_Type_Create("b4"); 01944 Operand(0, 0, 0, 6); // qp 01945 Operand(1, 0, 33, 2); // bwh 01946 Operand(2, 0, 12, 1); // ph 01947 Operand(3, 0, 35, 1); // dh 01948 Operand(4, 0, 13, 3); // b2 01949 Instruction_Pack_Group(b4, 01950 TOP_br_r_cond, 0x00100000000ULL, 01951 TOP_br_ret, 0x00108000100ULL, 01952 TOP_UNDEFINED); 01953 01954 /* ===== B4a: Indirect Branch ===== */ 01955 b4a = ISA_Pack_Type_Create("b4a"); 01956 Operand(0, 0, 33, 2); // bwh 01957 Operand(1, 0, 12, 1); // ph 01958 Operand(2, 0, 35, 1); // dh 01959 Operand(3, 0, 13, 3); // b2 01960 Instruction_Pack_Group(b4a, 01961 TOP_br_ia, 0x00100000040ULL, 01962 TOP_UNDEFINED); 01963 01964 /* ===== B5: Indirect Call ===== */ 01965 b5 = ISA_Pack_Type_Create("b5"); 01966 Operand(0, 0, 0, 6); // qp 01967 Operand(1, 0, 33, 2); // bwh 01968 Operand(2, 0, 12, 1); // ph 01969 Operand(3, 0, 35, 1); // dh 01970 Result(0, 6, 3); // b1 01971 Operand(4, 0, 13, 3); // b2 01972 Instruction_Pack_Group(b5, 01973 TOP_br_r_call, 0x02000000000ULL, 01974 TOP_UNDEFINED); 01975 01976 /* ===== B6: IP-Relative Predict ===== */ 01977 b6 = ISA_Pack_Type_Create("b6"); 01978 Operand(0, 0, 3, 2); // ipwh 01979 Operand(1, 0, 35, 1); // ih 01980 // Adjust_Operand(2, shr4, shl4); // imm_21 = target_25 >> 4 01981 Operand(2, 4, 13, 20); // imm_20b 01982 Operand(2, 24, 36, 1); // s 01983 // Adjust_Operand(3, shr4, shl4); // timm_9 = tag_13 >> 4 01984 Operand(3, 4, 6, 7); // timm_7a 01985 Operand(3, 11, 33, 2); // t_2e 01986 Instruction_Pack_Group(b6, 01987 TOP_brp, 0x0e000000000ULL, 01988 TOP_UNDEFINED); 01989 01990 /* ===== B7: Indirect Predict ===== */ 01991 b7 = ISA_Pack_Type_Create("b7"); 01992 Operand(0, 0, 3, 2); // indwh 01993 Operand(1, 0, 35, 1); // ih 01994 Operand(2, 0, 13, 3); // b2 01995 // Adjust_Operand(3, shr4, shl4); // timm_9 = tag_13 >> 4 01996 Operand(3, 4, 6, 7); // timm_7a 01997 Operand(3, 11, 33, 2); // t_2e 01998 Instruction_Pack_Group(b7, 01999 TOP_brp_r, 0x04080000000ULL, 02000 TOP_brp_ret, 0x04088000000ULL, 02001 TOP_UNDEFINED); 02002 02003 /* ===== B8: Miscellaneous ===== */ 02004 b8 = ISA_Pack_Type_Create("b8"); 02005 Instruction_Pack_Group(b8, 02006 TOP_cover, 0x00010000000ULL, 02007 TOP_clrrrb, 0x00020000000ULL, 02008 TOP_clrrrb_pr, 0x00028000000ULL, 02009 TOP_rfi, 0x00040000000ULL, 02010 TOP_bsw_0, 0x00060000000ULL, 02011 TOP_bsw_1, 0x00068000000ULL, 02012 TOP_epc, 0x00080000000ULL, 02013 TOP_UNDEFINED); 02014 02015 /* ===== B9: Break/Nop ===== */ 02016 b9 = ISA_Pack_Type_Create("b9"); 02017 Operand(0, 0, 0, 6); // qp 02018 Operand(1, 0, 6, 20); // imm_20a 02019 Operand(1, 20, 36, 1); // i 02020 Instruction_Pack_Group(b9, 02021 TOP_break_b, 0x00000000000ULL, 02022 TOP_nop_b, 0x04000000000ULL, 02023 TOP_UNDEFINED); 02024 02025 /* ===== B10: IP-Relative Unconditional Branch (pseudo) ===== */ 02026 b10 = ISA_Pack_Type_Create("b10"); 02027 Operand(0, 0, 12, 1); // ph 02028 Operand(1, 0, 35, 1); // dh 02029 // Adjust_Operand(2, shr4, shl4); // imm_21 = target_25 >> 4 02030 Operand(2, 4, 13, 20); // imm_20b 02031 Operand(2, 24, 36, 1); // s 02032 Instruction_Pack_Group(b10, 02033 TOP_br, 0x08000000000ULL, 02034 TOP_UNDEFINED); 02035 02036 /* ===== B11: Indirect Unconditional Branch (pseudo) ===== */ 02037 b11 = ISA_Pack_Type_Create("b11"); 02038 Operand(0, 0, 12, 1); // ph 02039 Operand(1, 0, 35, 1); // dh 02040 Operand(2, 0, 13, 3); // b2 02041 Instruction_Pack_Group(b11, 02042 TOP_br_r, 0x00100000000ULL, 02043 TOP_UNDEFINED); 02044 02045 /* ===== F1: Floating-point Multiply Add ===== */ 02046 f1 = ISA_Pack_Type_Create("f1"); 02047 Operand(0, 0, 0, 6); // qp 02048 Operand(1, 0, 34, 2); // sf 02049 Result(0, 6, 7); // f1 02050 Operand(2, 0, 20, 7); // f3 02051 Operand(3, 0, 27, 7); // f4 02052 Operand(4, 0, 13, 7); // f2 02053 Instruction_Pack_Group(f1, 02054 TOP_fma, 0x10000000000ULL, 02055 TOP_fma_s, 0x11000000000ULL, 02056 TOP_fma_d, 0x12000000000ULL, 02057 TOP_fpma, 0x13000000000ULL, 02058 TOP_fms, 0x14000000000ULL, 02059 TOP_fms_s, 0x15000000000ULL, 02060 TOP_fms_d, 0x16000000000ULL, 02061 TOP_fpms, 0x17000000000ULL, 02062 TOP_fnma, 0x18000000000ULL, 02063 TOP_fnma_s, 0x19000000000ULL, 02064 TOP_fnma_d, 0x1a000000000ULL, 02065 TOP_fpnma, 0x1b000000000ULL, 02066 TOP_UNDEFINED); 02067 02068 /* ===== F2: Fixed-point Multiply Add ===== */ 02069 f2 = ISA_Pack_Type_Create("f2"); 02070 Operand(0, 0, 0, 6); // qp 02071 Result(0, 6, 7); // f1 02072 Operand(1, 0, 20, 7); // f3 02073 Operand(2, 0, 27, 7); // f4 02074 Operand(3, 0, 13, 7); // f2 02075 Instruction_Pack_Group(f2, 02076 TOP_xma_l, 0x1d000000000ULL, 02077 TOP_xma_h, 0x1dc00000000ULL, 02078 TOP_xma_hu, 0x1d800000000ULL, 02079 TOP_UNDEFINED); 02080 02081 /* ===== F3: Parallel Floating-point Select ===== */ 02082 f3 = ISA_Pack_Type_Create("f3"); 02083 Operand(0, 0, 0, 6); // qp 02084 Result(0, 6, 7); // f1 02085 Operand(1, 0, 20, 7); // f3 02086 Operand(2, 0, 27, 7); // f4 02087 Operand(3, 0, 13, 7); // f2 02088 Instruction_Pack_Group(f3, 02089 TOP_fselect, 0x1c000000000ULL, 02090 TOP_UNDEFINED); 02091 02092 /* ===== F4: Floating-point Compare ===== */ 02093 f4 = ISA_Pack_Type_Create("f4"); 02094 Operand(0, 0, 0, 6); // qp 02095 Operand(1, 0, 34, 2); // sf 02096 Result(0, 6, 6); // p1 02097 Result(1, 27, 6); // p2 02098 Operand(2, 0, 13, 7); // f2 02099 Operand(3, 0, 20, 7); // f3 02100 Instruction_Pack_Group(f4, 02101 TOP_fcmp_eq, 0x08000000000ULL, 02102 TOP_fcmp_lt, 0x09000000000ULL, 02103 TOP_fcmp_le, 0x08200000000ULL, 02104 TOP_fcmp_unord, 0x09200000000ULL, 02105 TOP_fcmp_eq_unc, 0x08000001000ULL, 02106 TOP_fcmp_lt_unc, 0x09000001000ULL, 02107 TOP_fcmp_le_unc, 0x08200001000ULL, 02108 TOP_fcmp_unord_unc, 0x09200001000ULL, 02109 TOP_UNDEFINED); 02110 02111 /* ===== F5: Floating-point Class ===== */ 02112 f5 = ISA_Pack_Type_Create("f5"); 02113 Operand(0, 0, 0, 6); // qp 02114 Result(0, 6, 6); // p1 02115 Result(1, 27, 6); // p2 02116 Operand(1, 0, 13, 7); // f2 02117 Operand(2, 0, 33, 2); // fc_2 02118 Operand(2, 2, 20, 7); // fclass_7c 02119 Instruction_Pack_Group(f5, 02120 TOP_fclass_m, 0x0a000000000ULL, 02121 TOP_fclass_m_unc, 0x0a000001000ULL, 02122 TOP_UNDEFINED); 02123 02124 /* ===== F6: Floating-point Reciprocal Approximation ===== */ 02125 f6= ISA_Pack_Type_Create("f6"); 02126 Operand(0, 0, 0, 6); // qp 02127 Operand(1, 0, 34, 2); // sf 02128 Result(0, 6, 7); // f1 02129 Result(1, 27, 6); // p2 02130 Operand(2, 0, 13, 7); // f2 02131 Operand(3, 0, 20, 7); // f3 02132 Instruction_Pack_Group(f6, 02133 TOP_frcpa, 0x00200000000ULL, 02134 TOP_fprcpa, 0x02200000000ULL, 02135 TOP_UNDEFINED); 02136 02137 /* ===== F7: Floating-point Reciprocal Square Root Approximation ===== */ 02138 f7 = ISA_Pack_Type_Create("f7"); 02139 Operand(0, 0, 0, 6); // qp 02140 Operand(1, 0, 34, 2); // sf 02141 Result(0, 6, 7); // f1 02142 Result(1, 27, 6); // p2 02143 Operand(2, 0, 20, 7); // f3 02144 Instruction_Pack_Group(f7, 02145 TOP_frsqrta, 0x01200000000ULL, 02146 TOP_fprsqrta, 0x03200000000ULL, 02147 TOP_UNDEFINED); 02148 02149 /* ===== F8: Minimum/Maximum and Parallel Compare ===== */ 02150 f8 = ISA_Pack_Type_Create("f8"); 02151 Operand(0, 0, 0, 6); // qp 02152 Operand(1, 0, 34, 2); // sf 02153 Result(0, 6, 7); // f1 02154 Operand(2, 0, 13, 7); // f2 02155 Operand(3, 0, 20, 7); // f3 02156 Instruction_Pack_Group(f8, 02157 TOP_fmin, 0x000a0000000ULL, 02158 TOP_fmax, 0x000a8000000ULL, 02159 TOP_famin, 0x000b0000000ULL, 02160 TOP_famax, 0x000b8000000ULL, 02161 TOP_fpmin, 0x020a0000000ULL, 02162 TOP_fpmax, 0x020a8000000ULL, 02163 TOP_fpamin, 0x020b0000000ULL, 02164 TOP_fpamax, 0x020b8000000ULL, 02165 TOP_fpcmp_eq, 0x02180000000ULL, 02166 TOP_fpcmp_lt, 0x02188000000ULL, 02167 TOP_fpcmp_le, 0x02190000000ULL, 02168 TOP_fpcmp_unord, 0x02198000000ULL, 02169 TOP_fpcmp_neq, 0x021a0000000ULL, 02170 TOP_fpcmp_nlt, 0x021a8000000ULL, 02171 TOP_fpcmp_nle, 0x021b0000000ULL, 02172 TOP_fpcmp_ord, 0x021b8000000ULL, 02173 TOP_UNDEFINED); 02174 02175 /* ===== F9: Merge and Logical ===== */ 02176 f9 = ISA_Pack_Type_Create("f9"); 02177 Operand(0, 0, 0, 6); // qp 02178 Result(0, 6, 7); // f1 02179 Operand(1, 0, 13, 7); // f2 02180 Operand(2, 0, 20, 7); // f3 02181 Instruction_Pack_Group(f9, 02182 TOP_fmerge_s, 0x00080000000ULL, 02183 TOP_fmerge_ns, 0x00088000000ULL, 02184 TOP_fmerge_se, 0x00090000000ULL, 02185 TOP_fmix_lr, 0x001c8000000ULL, 02186 TOP_fmix_r, 0x001d0000000ULL, 02187 TOP_fmix_l, 0x001d8000000ULL, 02188 TOP_fsxt_r, 0x001e0000000ULL, 02189 TOP_fsxt_l, 0x001e8000000ULL, 02190 TOP_fpack, 0x00140000000ULL, 02191 TOP_fswap, 0x001a0000000ULL, 02192 TOP_fswap_nl, 0x001a8000000ULL, 02193 TOP_fswap_nr, 0x001b0000000ULL, 02194 TOP_fand, 0x00160000000ULL, 02195 TOP_fandcm, 0x00168000000ULL, 02196 TOP_for, 0x00170000000ULL, 02197 TOP_fxor, 0x00178000000ULL, 02198 TOP_fpmerge_s, 0x02080000000ULL, 02199 TOP_fpmerge_ns, 0x02088000000ULL, 02200 TOP_fpmerge_se, 0x02090000000ULL, 02201 TOP_UNDEFINED); 02202 02203 /* ===== F10: Convert Floating-point to Fixed-point ===== */ 02204 f10 = ISA_Pack_Type_Create("f10"); 02205 Operand(0, 0, 0, 6); // qp 02206 Operand(1, 0, 34, 2); // sf 02207 Result(0, 6, 7); // f1 02208 Operand(2, 0, 13, 7); // f2 02209 Instruction_Pack_Group(f10, 02210 TOP_fcvt_fx, 0x000c0000000ULL, 02211 TOP_fcvt_fxu, 0x000c8000000ULL, 02212 TOP_fcvt_fx_trunc, 0x000d0000000ULL, 02213 TOP_fcvt_fxu_trunc, 0x000d8000000ULL, 02214 TOP_fpcvt_fx, 0x020c0000000ULL, 02215 TOP_fpcvt_fxu, 0x020c8000000ULL, 02216 TOP_fpcvt_fx_trunc, 0x020d0000000ULL, 02217 TOP_fpcvt_fxu_trunc, 0x020d8000000ULL, 02218 TOP_UNDEFINED); 02219 02220 /* ===== F11: Convert Fixed-point to Floating-point ===== */ 02221 f11 = ISA_Pack_Type_Create("f11"); 02222 Operand(0, 0, 0, 6); // qp 02223 Result(0, 6, 7); // f1 02224 Operand(1, 0, 13, 7); // f2 02225 Instruction_Pack_Group(f11, 02226 TOP_fcvt_xf, 0x000e0000000ULL, 02227 TOP_UNDEFINED); 02228 02229 /* ===== F12: Floating-point Set Controls ===== */ 02230 f12 = ISA_Pack_Type_Create("f12"); 02231 Operand(0, 0, 0, 6); // qp 02232 Operand(1, 0, 34, 2); // sf 02233 Operand(2, 0, 13, 7); // amask_7b 02234 Operand(3, 0, 20, 7); // omask_7c 02235 Instruction_Pack_Group(f12, 02236 TOP_fsetc, 0x00020000000ULL, 02237 TOP_UNDEFINED); 02238 02239 /* ===== F13: Floating-point Clear Flags ===== */ 02240 f13 = ISA_Pack_Type_Create("f13"); 02241 Operand(0, 0, 0, 6); // qp 02242 Operand(1, 0, 34, 2); // sf 02243 Instruction_Pack_Group(f13, 02244 TOP_fclrf, 0x00028000000ULL, 02245 TOP_UNDEFINED); 02246 02247 /* ===== F14: Floating-point Check Flags ===== */ 02248 f14 = ISA_Pack_Type_Create("f14"); 02249 Operand(0, 0, 0, 6); // qp 02250 Operand(1, 0, 34, 2); // sf 02251 // Adjust_Operand(2, shr4, shl4); // imm_21 = target_25 >> 4 02252 Operand(2, 4, 6, 20); // imm_20a 02253 Operand(2, 24, 36, 1); // s 02254 Instruction_Pack_Group(f14, 02255 TOP_fchkf, 0x00040000000ULL, 02256 TOP_UNDEFINED); 02257 02258 /* ===== F15: Break/Nop ===== */ 02259 f15 = ISA_Pack_Type_Create("f15"); 02260 Operand(0, 0, 0, 6); // qp 02261 Operand(1, 0, 6, 20); // imm_20a 02262 Operand(1, 20, 36, 1); // i 02263 Instruction_Pack_Group(f15, 02264 TOP_break_f, 0x00000000000ULL, 02265 TOP_nop_f, 0x00008000000ULL, 02266 TOP_UNDEFINED); 02267 02268 /* ===== F16: Floating-point Absolute Value (pseudo) ===== */ 02269 f16 = ISA_Pack_Type_Create("f16"); 02270 Operand(0, 0, 0, 6); // qp 02271 Result(0, 6, 7); // f1 02272 Operand(1, 0, 20, 7); // f3 02273 Instruction_Pack_Group(f16, 02274 TOP_fabs, 0x00080000000ULL, 02275 TOP_fnegabs, 0x00088000000ULL, 02276 TOP_fpabs, 0x02080000000ULL, 02277 TOP_fpnegabs, 0x02088000000ULL, 02278 TOP_UNDEFINED); 02279 02280 /* ===== F17: Floating-point Negate (pseudo) ===== */ 02281 f17 = ISA_Pack_Type_Create("f17"); 02282 Operand(0, 0, 0, 6); // qp 02283 Result(0, 6, 7); // f1 02284 Operand(1, 0, 13, 7); // f3 02285 Operand(1, 0, 20, 7); // f3 02286 Instruction_Pack_Group(f17, 02287 TOP_fneg, 0x00088000000ULL, 02288 TOP_fpneg, 0x02088000000ULL, 02289 TOP_mov_f, 0x00080000000ULL, 02290 TOP_UNDEFINED); 02291 02292 /* ===== F18: Fixed-point Multiply Add (pseudo) ===== */ 02293 f18 = ISA_Pack_Type_Create("f18"); 02294 Operand(0, 0, 0, 6); // qp 02295 Result(0, 6, 7); // f1 02296 Operand(1, 0, 20, 7); // f3 02297 Operand(2, 0, 27, 7); // f4 02298 Operand(3, 0, 13, 7); // f2 02299 Instruction_Pack_Group(f18, 02300 TOP_xma_lu, 0x1d000000000ULL, 02301 TOP_UNDEFINED); 02302 02303 /* ===== F19: Fixed-point Multiply (pseudo) ===== */ 02304 f19 = ISA_Pack_Type_Create("f19"); 02305 Operand(0, 0, 0, 6); // qp 02306 Result(0, 6, 7); // f1 02307 Operand(1, 0, 20, 7); // f3 02308 Operand(2, 0, 27, 7); // f4 02309 Instruction_Pack_Group(f19, 02310 TOP_xmpy_l, 0x1d000000000ULL, 02311 TOP_xmpy_h, 0x1dc00000000ULL, 02312 TOP_xmpy_hu, 0x1d800000000ULL, 02313 TOP_xmpy_lu, 0x1d000000000ULL, 02314 TOP_UNDEFINED); 02315 02316 /* ===== F20: Convert Unsigned Integer to Floating-point (pseudo) ===== */ 02317 f20 = ISA_Pack_Type_Create("f20"); 02318 Operand(0, 0, 0, 6); // qp 02319 Operand(1, 0, 34, 2); // sf 02320 Result(0, 6, 7); // f1 02321 Operand(2, 0, 20, 7); // f3 02322 Instruction_Pack_Group(f20, 02323 TOP_fcvt_xuf, 0x10008000000ULL, 02324 TOP_fcvt_xuf_s, 0x11008000000ULL, 02325 TOP_fcvt_xuf_d, 0x12008000000ULL, 02326 TOP_fnorm, 0x10008000000ULL, 02327 TOP_fnorm_s, 0x11008000000ULL, 02328 TOP_fnorm_d, 0x12008000000ULL, 02329 TOP_UNDEFINED); 02330 02331 /* ===== F21: Floating-point Add/Subtract (pseudo) ===== */ 02332 f21 = ISA_Pack_Type_Create("f21"); 02333 Operand(0, 0, 0, 6); // qp 02334 Operand(1, 0, 34, 2); // sf 02335 Result(0, 6, 7); // f1 02336 Operand(2, 0, 20, 7); // f3 02337 Operand(3, 0, 13, 7); // f2 02338 Instruction_Pack_Group(f21, 02339 TOP_fadd, 0x10008000000ULL, 02340 TOP_fadd_s, 0x11008000000ULL, 02341 TOP_fadd_d, 0x12008000000ULL, 02342 TOP_fsub, 0x14008000000ULL, 02343 TOP_fsub_s, 0x15008000000ULL, 02344 TOP_fsub_d, 0x16008000000ULL, 02345 TOP_UNDEFINED); 02346 02347 /* ===== F22: Floating-point Multiply (pseudo) ===== */ 02348 f22 = ISA_Pack_Type_Create("f22"); 02349 Operand(0, 0, 0, 6); // qp 02350 Operand(1, 0, 34, 2); // sf 02351 Result(0, 6, 7); // f1 02352 Operand(2, 0, 20, 7); // f3 02353 Operand(3, 0, 27, 7); // f4 02354 Instruction_Pack_Group(f22, 02355 TOP_fmpy, 0x10000000000ULL, 02356 TOP_fmpy_s, 0x11000000000ULL, 02357 TOP_fmpy_d, 0x12000000000ULL, 02358 TOP_fnmpy, 0x18000000000ULL, 02359 TOP_fnmpy_s, 0x19000000000ULL, 02360 TOP_fnmpy_d, 0x1a000000000ULL, 02361 TOP_fpmpy, 0x13000000000ULL, 02362 TOP_fpnmpy, 0x1b000000000ULL, 02363 TOP_UNDEFINED); 02364 02365 /* ===== F23: Floating-point Class (pseudo) ===== */ 02366 f23 = ISA_Pack_Type_Create("f23"); 02367 Operand(0, 0, 0, 6); // qp 02368 Result(0, 27, 6); // p2 02369 Result(1, 6, 6); // p1 02370 Operand(1, 0, 13, 7); // f2 02371 Operand(2, 0, 33, 2); // fc_2 02372 Operand(2, 2, 20, 7); // fclass_7c 02373 Instruction_Pack_Group(f23, 02374 TOP_fclass_nm, 0x0a000000000ULL, 02375 TOP_fclass_nm_unc, 0x0a000001000ULL, 02376 TOP_UNDEFINED); 02377 02378 /* ===== F24: Floating-point Compare (pseudo) ===== */ 02379 // swapped args 02380 f24 = ISA_Pack_Type_Create("f24"); 02381 Operand(0, 0, 0, 6); // qp 02382 Operand(1, 0, 34, 2); // sf 02383 Result(0, 6, 6); // p1 02384 Result(1, 27, 6); // p2 02385 Operand(2, 0, 20, 7); // f3 02386 Operand(3, 0, 13, 7); // f2 02387 Instruction_Pack_Group(f24, 02388 TOP_fcmp_gt, 0x09000000000ULL, 02389 TOP_fcmp_ge, 0x08200000000ULL, 02390 TOP_fcmp_gt_unc, 0x09000001000ULL, 02391 TOP_fcmp_ge_unc, 0x08200001000ULL, 02392 TOP_UNDEFINED); 02393 02394 /* ===== F25: Floating-point Compare (pseudo) ===== */ 02395 // swapped preds 02396 f25 = ISA_Pack_Type_Create("f25"); 02397 Operand(0, 0, 0, 6); // qp 02398 Operand(1, 0, 34, 2); // sf 02399 Result(0, 27, 6); // p2 02400 Result(1, 6, 6); // p1 02401 Operand(2, 0, 13, 7); // f2 02402 Operand(3, 0, 20, 7); // f3 02403 Instruction_Pack_Group(f25, 02404 TOP_fcmp_neq, 0x08000000000ULL, 02405 TOP_fcmp_nlt, 0x09000000000ULL, 02406 TOP_fcmp_nle, 0x08200000000ULL, 02407 TOP_fcmp_ord, 0x09200000000ULL, 02408 TOP_fcmp_neq_unc, 0x08000001000ULL, 02409 TOP_fcmp_nlt_unc, 0x09000001000ULL, 02410 TOP_fcmp_nle_unc, 0x08200001000ULL, 02411 TOP_fcmp_ord_unc, 0x09200001000ULL, 02412 TOP_UNDEFINED); 02413 02414 /* ===== F26: Floating-point Compare (pseudo) ===== */ 02415 // swapped args and preds 02416 f26 = ISA_Pack_Type_Create("f26"); 02417 Operand(0, 0, 0, 6); // qp 02418 Operand(1, 0, 34, 2); // sf 02419 Result(0, 27, 6); // p2 02420 Result(1, 6, 6); // p1 02421 Operand(2, 0, 20, 7); // f3 02422 Operand(3, 0, 13, 7); // f2 02423 Instruction_Pack_Group(f26, 02424 TOP_fcmp_ngt, 0x09000000000ULL, 02425 TOP_fcmp_nge, 0x08200000000ULL, 02426 TOP_fcmp_ngt_unc, 0x09000001000ULL, 02427 TOP_fcmp_nge_unc, 0x08200001000ULL, 02428 TOP_UNDEFINED); 02429 02430 /* ===== F27: Floating-point Parallel Compare (pseudo) ===== */ 02431 // swapped args 02432 f27 = ISA_Pack_Type_Create("f27"); 02433 Operand(0, 0, 0, 6); // qp 02434 Operand(1, 0, 34, 2); // sf 02435 Result(0, 6, 7); // f1 02436 Operand(2, 0, 20, 7); // f3 02437 Operand(3, 0, 13, 7); // f2 02438 Instruction_Pack_Group(f27, 02439 TOP_fpcmp_gt, 0x02188000000ULL, 02440 TOP_fpcmp_ge, 0x02190000000ULL, 02441 TOP_fpcmp_ngt, 0x021a8000000ULL, 02442 TOP_fpcmp_nge, 0x021b0000000ULL, 02443 TOP_UNDEFINED); 02444 02445 /* ===== X1: Break/Nop ===== */ 02446 x1 = ISA_Pack_Type_Create("x1"); 02447 Operand(1, 21, 0, 41); // imm_41 02448 Next_Word(); 02449 Operand(0, 0, 0, 6); // qp 02450 Operand(1, 0, 6, 20); // imm_20a 02451 Operand(1, 20, 36, 1); // i 02452 Instruction_Pack_Group(x1, 02453 TOP_break_x, 0x00000000000ULL, 0x00000000000ULL, 02454 TOP_nop_x, 0x00000000000ULL, 0x00008000000ULL, 02455 TOP_UNDEFINED); 02456 02457 /* ===== X2: Move Long Immediate_64 ===== */ 02458 x2 = ISA_Pack_Type_Create("x2"); 02459 Operand(1, 22, 0, 41); // imm_41 02460 Next_Word(); 02461 Operand(0, 0, 0, 6); // qp 02462 Result(0, 6, 7); // r1 02463 Operand(1, 0, 13, 7); // imm_7b 02464 Operand(1, 7, 27, 9); // imm_9d 02465 Operand(1, 16, 22, 5); // imm_5c 02466 Operand(1, 21, 21, 1); // ic 02467 Operand(1, 63, 36, 1); // i 02468 Instruction_Pack_Group(x2, 02469 TOP_movl, 0x00000000000ULL, 0x0c000000000ULL, 02470 TOP_UNDEFINED); 02471 02472 /* ===== X3: Long Branch ===== */ 02473 x3 = ISA_Pack_Type_Create("x3"); 02474 // Adjust_Operand(4, shr4, shl4); // imm_60 = target_64 >> 4 02475 Operand(4, 24, 2, 39); // imm_39 02476 Next_Word(); 02477 Operand(0, 0, 0, 6); // qp 02478 Operand(1, 0, 33, 2); // bwh 02479 Operand(2, 0, 12, 1); // ph 02480 Operand(3, 0, 35, 1); // dh 02481 Operand(4, 4, 13, 20); // imm_20b 02482 Operand(4, 63, 36, 1); // i 02483 Instruction_Pack_Group(x3, 02484 TOP_brl_cond, 0x00000000000ULL, 0x18000000000ULL, 02485 TOP_UNDEFINED); 02486 02487 /* ===== X4: Long Call ===== */ 02488 x4 = ISA_Pack_Type_Create("x4"); 02489 // Adjust_Operand(4, shr4, shl4); // imm_60 = target_64 >> 4 02490 Operand(4, 24, 2, 39); // imm_39 02491 Next_Word(); 02492 Operand(0, 0, 0, 6); // qp 02493 Operand(1, 0, 33, 2); // bwh 02494 Operand(2, 0, 12, 1); // ph 02495 Operand(3, 0, 35, 1); // dh 02496 Result(0, 6, 3); // b1 02497 Operand(4, 4, 13, 20); // imm_20b 02498 Operand(4, 63, 36, 1); // i 02499 Instruction_Pack_Group(x4, 02500 TOP_brl_call, 0x00000000000ULL, 0x1a000000000ULL, 02501 TOP_UNDEFINED); 02502 02503 /* ===== X5: Long Branch (pseudo) ===== */ 02504 x5 = ISA_Pack_Type_Create("x5"); 02505 // Adjust_Operand(2, shr4, shl4); // imm_60 = target_64 >> 4 02506 Operand(2, 24, 2, 39); // imm_39 02507 Next_Word(); 02508 Operand(0, 0, 12, 1); // ph 02509 Operand(1, 0, 35, 1); // dh 02510 Operand(2, 4, 13, 20); // imm_20b 02511 Operand(2, 63, 36, 1); // i 02512 Instruction_Pack_Group(x5, 02513 TOP_brl, 0x00000000000ULL, 0x18000000000ULL, 02514 TOP_UNDEFINED); 02515 02516 ISA_Pack_End(); 02517 return 0; 02518 }
1.7.6.1 
