Open64 (mfef90, whirl2f, and IR tools)
TAG: version-openad; SVN changeset: 916
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00001 /* 00002 00003 Copyright (C) 2000, 2001 Silicon Graphics, Inc. All Rights Reserved. 00004 00005 This program is free software; you can redistribute it and/or modify it 00006 under the terms of version 2 of the GNU General Public License as 00007 published by the Free Software Foundation. 00008 00009 This program is distributed in the hope that it would be useful, but 00010 WITHOUT ANY WARRANTY; without even the implied warranty of 00011 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 00012 00013 Further, this software is distributed without any warranty that it is 00014 free of the rightful claim of any third person regarding infringement 00015 or the like. Any license provided herein, whether implied or 00016 otherwise, applies only to this software file. Patent licenses, if 00017 any, provided herein do not apply to combinations of this program with 00018 other software, or any other product whatsoever. 00019 00020 You should have received a copy of the GNU General Public License along 00021 with this program; if not, write the Free Software Foundation, Inc., 59 00022 Temple Place - Suite 330, Boston MA 02111-1307, USA. 00023 00024 Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pky, 00025 Mountain View, CA 94043, or: 00026 00027 http://www.sgi.com 00028 00029 For further information regarding this notice, see: 00030 00031 http://oss.sgi.com/projects/GenInfo/NoticeExplan 00032 00033 */ 00034 00035 00036 /* ==================================================================== 00037 * ==================================================================== 00038 * 00039 * 00040 * Synopsis: 00041 * 00042 * Instruction latency information, i.e. the cycles at which 00043 * key events occur. 00044 * 00045 * Interface Description: 00046 * 00047 * Exported functions: 00048 * 00049 * INT TI_LATENCY_Load_Cycle( 00050 * TOP opcode 00051 * ) 00052 * 00053 * The cycle in which an operand is loaded from memory. 00054 * 00055 * INT TI_LATENCY_Store_Cycle( 00056 * TOP opcode 00057 * ) 00058 * 00059 * The cycle in which a value is stored to memory. 00060 * 00061 * INT TI_LATENCY_Last_Issue_Cycle( 00062 * TOP opcode 00063 * ) 00064 * 00065 * The last issue cycle for the given operation. 00066 * 00067 * INT TI_LATENCY_Commit_Cycle( 00068 * TOP opcode 00069 * ) 00070 * 00071 * The cycle in which the operation is fully committed, 00072 * i.e. no machine exceptions or other events will 00073 * prevent its completion. For branches, this is interpreted 00074 * as the last cycle before instructions from the branch 00075 * target, instead of the shadow, begin being issued. 00076 * 00077 * INT TI_LATENCY_Operand_Access_Cycle( 00078 * TOP opcode 00079 * INT opnd 00080 * ) 00081 * 00082 * The cycle in which operand number 'opnd' is read from 00083 * a register. 00084 * 00085 * INT TI_LATENCY_Result_Available_Cycle( 00086 * TOP opcode 00087 * INT result 00088 * ) 00089 * 00090 * The cycle in which result number 'result' is written to 00091 * a register. 00092 * 00093 * Instruction latencies, i.e. hazards, are things to avoid. 00094 * Unfortunately, the MIPS architecture did not take this advice 00095 * to heart, so we need to be able to keep certain ops away from 00096 * one another. To do so, we use: 00097 * 00098 * INT TI_LATENCY_Operand_Hazard( 00099 * TOP opcode 00100 * INT *opnd 00101 * INT *error 00102 * ) 00103 * 00104 * If 'opcode' has an operand hazard, the operand number 00105 * is returned by reference through 'opnd' and the function 00106 * return value indicates the size (in instructions) 00107 * and direction of the hazard. The absolute value 00108 * of the return value indicates how many instructions 00109 * must precede (negative return value) or follow 00110 * (positive return value) before the operand can be 00111 * written by another instruction. 00112 * 00113 * A return value of 0 indicates there is no operand 00114 * hazard for 'opcode'. 00115 * If an error occurs, 'error' will be set to TI_RC_ERROR. 00116 * 00117 * INT TI_LATENCY_Result_Hazard( 00118 * TOP opcode 00119 * INT *result 00120 * INT *error 00121 * ) 00122 * 00123 * If 'opcode' has a result hazard, the result number 00124 * is returned by reference through 'result' and the function 00125 * return value indicates how many instructions must follow 00126 * before the result can be referenced. 00127 * 00128 * A return value of 0 indicates there is no result 00129 * hazard for 'opcode'. 00130 * If an error occurs, 'error' will be set to TI_RC_ERROR. 00131 * 00132 * INT TI_LATENCY_Errata_Hazard( 00133 * TOP opcode 00134 * INT *number 00135 * INT *error 00136 * ) 00137 * 00138 * Errata hazards identify particular bugs in the hardware 00139 * that must be worked around. The return value indicates if 00140 * 'opcode' has an errata hazard and represents the size of 00141 * the hazard (in instructions). The particular errata number 00142 * of the hazard is returned through the out parameter 00143 * 'number'. 00144 * 00145 * A return value of 0 indicates there is no errata 00146 * hazard for 'opcode'. 00147 * If an error occurs, 'error' will be set to TI_RC_ERROR. 00148 * 00149 * ==================================================================== 00150 * ==================================================================== 00151 */ 00152 00153 #ifndef ti_latency_INCLUDED 00154 #define ti_latency_INCLUDED 00155 00156 #include "topcode.h" 00157 #include "ti_si.h" 00158 00159 #ifdef __cplusplus 00160 extern "C" { 00161 #endif 00162 00163 #ifdef _KEEP_RCS_ID 00164 #endif /* _KEEP_RCS_ID */ 00165 00166 inline INT TI_LATENCY_Load_Cycle(TOP opcode) 00167 { 00168 return TSI_Load_Access_Time(opcode); 00169 } 00170 00171 inline INT TI_LATENCY_Store_Cycle(TOP opcode) 00172 { 00173 return TSI_Store_Available_Time(opcode); 00174 } 00175 00176 inline INT TI_LATENCY_Operand_Access_Cycle(TOP opcode, INT opnd) 00177 { 00178 return TSI_Operand_Access_Time(opcode, opnd); 00179 } 00180 00181 inline INT TI_LATENCY_Result_Available_Cycle(TOP opcode, INT result) 00182 { 00183 return TSI_Result_Available_Time(opcode, result); 00184 } 00185 00186 inline INT TI_LATENCY_Last_Issue_Cycle(TOP opcode) 00187 { 00188 return TSI_Last_Issue_Cycle(opcode); 00189 } 00190 00191 extern INT TI_LATENCY_Commit_Cycle(TOP opcode); 00192 extern INT TI_LATENCY_Operand_Hazard(TOP opcode, INT *opnd, INT *error); 00193 extern INT TI_LATENCY_Result_Hazard(TOP opcode, INT *result, INT *error); 00194 extern INT TI_LATENCY_Errata_Hazard(TOP opcode, INT *number, INT *error); 00195 00196 #ifdef __cplusplus 00197 } 00198 #endif 00199 #endif /* ti_latency_INCLUDED */