Seminars & Events

Mathematics and Computer Science Division
" Cross-Layer Customization onto High-Performance Multi-Core/Many-Core Processors"

DATE: October 7, 2010
TIME: 10:30 AM - 11:30 AM
SPEAKER: Chenjie Yu, RADIX Postdoc
LOCATION: Building 240 Seminar Room 4301, Argonne National Laboratory
HOST: Kamil Iskra

Description:
Due to physical constraints and design difficulties, the computer processor architectures have shifted to multi-core and many-core based approaches in recent years. Today, chip multi-processor (CMP)products are replacing uni-processors in every segment of the market, including super computers, with the capability to integrate hundreds of cores onto individual chips. This provides tremendous potential towards peta/exa-scale computing platforms.
However, people in both academia research and industry are still seeking proper ways to make efficient and effective use of these processor architectures. The impact to the user software and system software development is largely under exploration. However, little has been settled for large scale CMPs architecture, system software, and applications, which also means research opportunities in this field.
In this talk, I will briefly go over the development and architecture issues of CMP architectures and its applications. Through the example of Tilera processors, I would like to share some insights about software development and performance optimization onto mid-large scale CMPs. I will also present a cache partitioning technique for reducing memory bandwidth requirement on CMP platforms.

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