Seminar Details:

LANS Informal Seminar
"Process Variation Aware Thread Mapping for Chip Multiprocessors"

DATE: March 25, 2009

TIME: 15:00:00 - 16:00:00
SPEAKER: Sri Hari Krishna Narayanan, MCS
LOCATION: Building 221, Room A216, Argonne National Laboratory

Description:
With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that identically-designed processor cores on the chip have non-identical peak frequencies and power consumptions. To cope with such a design, each processor can be assumed to run at the frequency of the slowest processor, resulting in wasted computational capability. This talk considers an alternate approach and proposes an algorithm that intelligently maps (and remaps) computations onto available processors so that each processor runs at its peak frequency.


 

Please send questions or suggestions to Debojyoti Ghosh: ghosh at mcs dot anl dot gov.