LANS Research


TUNE : Compiler-Directed Automatic Performance Tuning

Paul Hovland

MCS People Involved:
Jaewook Shin

Additional People:
Mary Hall, Utah (Lead PI) , Jacqueline Chame, ISI (co-PI) , Chun Chen, Utah

Other Institutes:
University of Utah , USC Information Sciences Institute


In this project, we will develop compiler-directed performance tuning technology
targeting the Cray XT3 system at Oak Ridge, which has multi-core Opteron nodes with
SSE-3 SIMD extensions. To achieve this goal, we will combine compiler infrastructures
for model-guided empirical optimization for memory hierarchy and SIMD code
generation, which have been developed by the PIs over the past several years. We will work
with DOE Office of Science applications to identify performance bottlenecks, and apply
our system to computational kernels that operate on dense arrays. Our goal for this
performance-tuning technology is to yield hand-tuned levels of performance on DOE
Office of Science computational kernels, while allowing application programmers to
specify their computations at a high-level without requiring manual optimization. Prior
results for the related Intel Pentium show hand-tuned levels of performance for linear
algebra computations.