cache disabled

Usually all cache and prefetching mechanism are enabled. We have disabled cache by changing Memory Type Range Registers(MTRR) through /proc/mtrr. By default, normal memory region is set to "write-back". We simply changed it to "uncachable", which shows very big difference between large page and small page and large page always has better performance than small one. Of course, the overall performance is completely bad because of no cache.

Actually we also disabled a x86 hardware prefetch mechanism called DPL by modifiying one of MSR regisiters. However, we recognized that DPL helps stream access for 4KB page but it doesn't show significant difference. There is another prefetch mechanism called L2 Streamer (Adjacent Cache Line Prefetch) but this is not available on our test machine(Pentium-4M).

cache disabled

cache enabled(normal)

cache disabled

reference

cache disabled

reference