Accelerators and Hybrid Exascale Systems (AsHES)
To be held in conjunction with
IPDPS 2015: IEEE International Parallel and Distributed Processing Symposium
New short format papers will be accepted.
Workshop Scope and Goals
As we look beyond the petascale era, accelerator and heterogeneous architectures are expected to play a preeminent role in architecting the largest systems in the world. Future systems may not only offer accelerators (e.g. GPGPU, Intel® Xeon Phi™, FPGA) and hybrid processors of both lightweight and heavyweight cores (e.g APU, big.LITTLE), but also may use hybrid memory systems equipped with stacked memory and non-volatile memory in addition to regular DRAM. While there is significant interest in these architectures, much of it is an artifact of the hype associated with them. This workshop focuses on understanding the implications of accelerators and heterogeneous designs on the hardware systems, applications, and programming environments of future systems. It seeks to ground accelerator research through studies of application kernels or whole applications on such systems, as well as tools and libraries that improve the performance and productivity of applications on these systems.
The goal of this workshop is to bring together researchers and practitioners who are involved in application studies for accelerators and other heterogeneous systems, to learn the opportunities and challenges in future design trends for HPC applications and systems.
Jan. 10 Jan. 17 Jan. 28, 2015 AoE
Author Notification: Feb. 14, 2015
Camera-Ready Deadline: Feb. 28, 2015
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