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Open64 (mfef90, whirl2f, and IR tools)
TAG: version-openad; SVN changeset: 916
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Open64 (mfef90, whirl2f, and IR tools)
TAG: version-openad; SVN changeset: 916
|
Go to the source code of this file.
Defines | |
| #define | ZERO64(a) ( (a).part1 = (a).part2 = (a).part3 = (a).part4 = 0 ) |
| #define | COPY64(to, fr) |
| #define | SHLEFT64(x) |
| #define | SHLEFT64N(x, n) |
| #define | SHRIGHT64(x) |
| #define | SHRIGHT64N(x, n) |
| #define | SHRIGHT64X(x) |
| #define | SIGNBIT(x) ( (x).part1 >> 15 ) |
| #define | ADD64(sum, a, b) |
| #define | INC64(a) |
| #define | DEC64(a) |
| #define | NEG64(a) |
| #define | MULSTEP(sum, bits, val, ct) |
| #define | NOT64(a) |
| #define | WORD_SWAP(x) |
| #define ADD64 | ( | sum, | |
| a, | |||
| b | |||
| ) |
do { \ unsigned long t = (a).part4 + (b).part4; \ (sum).part4 = t; \ t >>= 16; \ (sum).part3 = t += (a).part3 + (b).part3; \ t >>= 16; \ (sum).part2 = t += (a).part2 + (b).part2; \ (sum).part1 = (t >> 16) + (a).part1 + (b).part1; \ } while (0)
Definition at line 164 of file int64.h.
Referenced by ar_c1frecip(), and ar_sim().
| #define COPY64 | ( | to, | |
| fr | |||
| ) |
( (to).part1 = (fr).part1, \
(to).part2 = (fr).part2, \
(to).part3 = (fr).part3, \
(to).part4 = (fr).part4 )
Definition at line 49 of file int64.h.
Referenced by ar_c1frecip(), ar_cflt128(), ar_cflt64(), ar_iflt128(), ar_iflt32(), ar_iflt64(), and ar_sim().
| #define DEC64 | ( | a | ) |
do { \ unsigned long t = (a).part4 + MASKR (16); \ (a).part4 = t; \ (a).part3 = t = (t >> 16) + (a).part3 + MASKR (16); \ (a).part2 = t = (t >> 16) + (a).part2 + MASKR (16); \ (a).part1 += (t >> 16) + MASKR (16); \ } while (0)
Definition at line 190 of file int64.h.
Referenced by ar_ifix128(), ar_ifix32(), and ar_ifix64().
| #define INC64 | ( | a | ) |
do { \ unsigned long t = (a).part4 + 1; \ (a).part4 = t; \ (a).part3 = t = (t >> 16) + (a).part3; \ (a).part2 = t = (t >> 16) + (a).part2; \ (a).part1 += t >> 16; \ } while (0)
Definition at line 178 of file int64.h.
Referenced by ar_c1frecip(), ar_cfix128(), ar_cfix64(), ar_ifix128(), ar_ifix32(), and ar_ifix64().
| #define NEG64 | ( | a | ) |
do { \ NOT64 (a); \ INC64 (a); \ } while (0)
Definition at line 202 of file int64.h.
Referenced by ar_cflt128(), ar_cflt64(), ar_iflt128(), ar_iflt32(), ar_iflt64(), ar_set_invalid_result(), and ar_sim().
| #define NOT64 | ( | a | ) |
( (a).part1 ^= MASKR (16), \ (a).part2 ^= MASKR (16), \ (a).part3 ^= MASKR (16), \ (a).part4 ^= MASKR (16) )
Definition at line 221 of file int64.h.
Referenced by ar_c1frecip(), ar_cfix128(), ar_cfix64(), ar_ifix128(), ar_ifix32(), ar_ifix64(), and ar_sim().
| #define SHLEFT64 | ( | x | ) |
do { \ (x).part1 = ((x).part1 << 1) | ((x).part2 >> 15); \ (x).part2 = ((x).part2 << 1) | ((x).part3 >> 15); \ (x).part3 = ((x).part3 << 1) | ((x).part4 >> 15); \ (x).part4 = (x).part4 << 1; \ } while (0)
Definition at line 58 of file int64.h.
Referenced by ar_c1frecip(), ar_cfix128(), ar_cfix64(), ar_ifix32(), ar_ifix64(), and ar_sim().
| #define SHLEFT64N | ( | x, | |
| n | |||
| ) |
do { \ register int _n = n; \ switch(_n>>4){ \ case 0: \ (x).part1 = ((x).part1 << _n) | ((x).part2 >> (16-_n)); \ (x).part2 = ((x).part2 << _n) | ((x).part3 >> (16-_n)); \ (x).part3 = ((x).part3 << _n) | ((x).part4 >> (16-_n)); \ (x).part4 = ((x).part4 << _n); \ break; \ case 1: \ (x).part1 = ((x).part2 << (_n-16)) | ((x).part3 >> (32-_n));\ (x).part2 = ((x).part3 << (_n-16)) | ((x).part4 >> (32-_n));\ (x).part3 = ((x).part4 << (_n-16)); \ (x).part4 = 0; \ break; \ case 2: \ (x).part1 = ((x).part3 << (_n-32)) | ((x).part4 >> (48-_n));\ (x).part2 = ((x).part4 << (_n-32)); \ (x).part3 = (x).part4 = 0; \ break; \ case 3: \ (x).part1 = ((x).part4 << (_n-48)); \ (x).part2 = (x).part3 = (x).part4 = 0; \ break; \ default: \ (x).part1 = (x).part2 = (x).part3 = (x).part4 = 0; \ } \ } while(0)
Definition at line 69 of file int64.h.
Referenced by ar_sim().
| #define SHRIGHT64 | ( | x | ) |
do { \ (x).part4 = ((x).part4 >> 1) | (((x).part3 & 1) << 15); \ (x).part3 = ((x).part3 >> 1) | (((x).part2 & 1) << 15); \ (x).part2 = ((x).part2 >> 1) | (((x).part1 & 1) << 15); \ (x).part1 >>= 1; \ } while (0)
Definition at line 102 of file int64.h.
Referenced by ar_c1frecip(), ar_cflt128(), ar_cflt64(), ar_ifix128(), ar_ifix32(), ar_ifix64(), ar_iflt32(), ar_power(), and ar_sim().
| #define SHRIGHT64N | ( | x, | |
| n | |||
| ) |
do { \ register int _n = n; \ switch(_n>>4) { \ case 0: \ (x).part4 = ((x).part4 >> _n) | ((x).part3 << (16-_n)); \ (x).part3 = ((x).part3 >> _n) | ((x).part2 << (16-_n)); \ (x).part2 = ((x).part2 >> _n) | ((x).part1 << (16-_n)); \ (x).part1 = ((x).part1 >> _n); \ break; \ case 1: \ (x).part4 = ((x).part3 >> (_n-16)) | ((x).part2 << (32-_n));\ (x).part3 = ((x).part2 >> (_n-16)) | ((x).part1 << (32-_n));\ (x).part2 = ((x).part1 >> (_n-16)); \ (x).part1 = 0; \ break; \ case 2: \ (x).part4 = ((x).part2 >> (_n-32)) | ((x).part1 << (48-_n));\ (x).part3 = ((x).part1 >> (_n-32)); \ (x).part2 = (x).part1 = 0; \ break; \ case 3: \ (x).part4 = ((x).part1 >> (_n-48)); \ (x).part3 = (x).part2 = (x).part1 = 0; \ break; \ default: \ (x).part4 = (x).part3 = (x).part2 = (x).part1 = 0; \ } \ } while(0)
Definition at line 113 of file int64.h.
Referenced by ar_sim().
| #define SHRIGHT64X | ( | x | ) |
do { \ (x).part4 = ((x).part4 >> 1) | (((x).part3 & 1) << 15); \ (x).part3 = ((x).part3 >> 1) | (((x).part2 & 1) << 15); \ (x).part2 = ((x).part2 >> 1) | (((x).part1 & 1) << 15); \ (x).part1 = ((x).part1 >> 1) | ((x).part1 & (1 << 15)); \ } while (0)
Definition at line 147 of file int64.h.
Referenced by ar_cfix128(), and ar_cfix64().
| #define SIGNBIT | ( | x | ) | ( (x).part1 >> 15 ) |
Definition at line 158 of file int64.h.
Referenced by ar_cflt128(), ar_cflt64(), ar_iflt128(), ar_iflt32(), and ar_iflt64().
| #define ZERO64 | ( | a | ) | ( (a).part1 = (a).part2 = (a).part3 = (a).part4 = 0 ) |
Definition at line 43 of file int64.h.
Referenced by ar_c1frecip(), ar_cfix128(), ar_cfix64(), ar_clear_sim_state(), ar_convert_str_to_float(), ar_ifix128(), ar_ifix32(), ar_ifix64(), ar_pass_arg_address(), ar_pass_ext_address(), ar_set_invalid_result(), and ar_sim().
1.7.6.1