Accelerators and Hybrid Exascale Systems (AsHES)
To be held in conjunction with
IPDPS 2015: IEEE International Parallel and Distributed Processing Symposium
As we look beyond the petascale era, accelerator and heterogeneous architectures are expected to play a preeminent role in architecting the largest systems in the world. Future systems may not only offer accelerators (e.g. GPGPU, Intel® Xeon Phi™, FPGA) and hybrid processors of both lightweight and heavyweight cores (e.g APU, big.LITTLE), but also may use hybrid memory systems equipped with stacked memory and non-volatile memory in addition to regular DRAM. While there is significant interest in these architectures, much of it is an artifact of the hype associated with them. This workshop focuses on understanding the implications of accelerators and heterogeneous designs on the hardware systems, applications, and programming environments of future systems. It seeks to ground accelerator research through studies of application kernels or whole applications on such systems, as well as tools and libraries that improve the performance and productivity of applications on these systems.
The goal of this workshop is to bring together researchers and practitioners who are involved in application studies for accelerators and heterogeneous systems, to learn the opportunities and challenges in future design trends for HPC applications and systems.
We are soliciting contributions in areas including but not limited to:
- Strategies for application behavior characterization and performance optimization for accelerators;
- Techniques for optimizing kernels for execution on GPGPU, Intel® Xeon Phi™, and future heterogeneous platforms;
- Models of application performance on heterogeneous and accelerated HPC systems;
- Implications of workload characterization in heterogeneous and accelerated architecture design;
- Benchmarking and performance evaluation for accelerators;
- Tools and techniques to assist application development for accelerators and heterogeneous processors;
- System software techniques to abstract application domain-specific functionalities for accelerators.
The proceedings of this workshop will be published electronically together with with IPDPS proceedings via the IEEE Xplore Digital Library.
Submitted manuscripts may not exceed 10 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references. See the style templates for latex or word for details.
Short format papers at least 5 pages in length will also be accepted.
Submissions will be judged based on relevance, significance, originality, correctness and clarity.
Submissions can be made at this link.
Journal Special Issue
The best papers of AsHES 2015 will be included in a Special Issue on Applications for the Heterogeneous Computing Era of the International Journal of High Performance Computing Applications.
Jan. 10 Jan. 17 Jan. 28, 2015 AoE
Author Notification: Feb. 14, 2015
Camera-Ready Deadline: Feb. 28, 2015
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