The Fourth International Workshop on
Accelerators and Hybrid Exascale Systems (AsHES)
Accelerators and Hybrid Exascale Systems (AsHES)
Join us on May 19th, 2014 in Phoenix, USA
To be held in conjunction with
IPDPS 2014: IEEE International Parallel and Distributed Processing Symposium
To be held in conjunction with
IPDPS 2014: IEEE International Parallel and Distributed Processing Symposium
Opening remarks
8:30 - 8:45 am
Keynote by Jeffrey Vetter: Exploring Emerging Technologies in the HPC Co-Design Space
8:45 - 9:50 am
SlidesAbstract: Concerns about energy-efficiency and reliability have forced our community to reexamine the full spectrum of architectures, software, and algorithms that constitute our ecosystem. While architectures and programming models remained relatively stable for almost two decades, new architectural features, such as heterogeneous processing, nonvolatile memory, and optical interconnection networks, will demand that applications be redesigned so that they expose massive amounts of hierarchical parallelism, carefully orchestrate data movement, and balance concerns over accuracy, reliability, and time to solution. In what we have termed 'co-design,' teams of architects, software designers, and applications scientists, are working collectively to realize an integrated solution to these challenges. Not surprisingly, this design space can be massive and uncertain. To assist in this design space exploration, our team is using modeling, simulation, and measurement on prototype systems in order to assess the possible trajectories of these future systems. In this talk, I will sample these emerging technologies and discuss how we are preparing for these upcoming systems.
Break 9:50 - 10:20 am
Session 1: Programing Model and Performance Optimizations (Chair: Karthikeyan Vaidyanathan, Intel)
10:20 am - 12:00 pm
- Scalable Critical Path Analysis for Hybrid MPI-CUDA Applications Felix Schmitt, Robert Dietrich and Guido Juckeland Slides
- Dymaxion++: a Directive-Based API to Optimize Data Layout and Memory Mapping for Heterogeneous Systems Shuai Che, Jiayuan Meng and Kevin Skadron
- Comparison of Parallel Programming Models on Intel MIC Computer Cluster Chenggang Lai, Zhijun Hao, Miaoqing Huang, Xuan Shi and Haihang You Slides
- CoAdELL: Adaptivity and Compression for Improving Sparse Matrix-Vector Multiplication on GPUs Marco Maggioni and Tanya Berger-Wolf Slides
Lunch 12:00 - 1:30 pm
Session 2: Accelerating Applications (Chair: Sunita Chandrasekaran, University of Houston)
1:30 - 3:10 pm
- Optimizing Krylov Subspace Solvers on Graphics Processing Units Hartwig Anzt, William Sawyer, Stanimire Tomov, Piotr Luszczek, Ichitaro Yamazaki and Jack Dongarra Slides
- XSW: Accelerating Biological Database Search on Xeon Phi Lipeng Wang, Yuandong Chan, Xiaohui Duan, Haidong Lan, Xiangxu Meng and Weiguo Liu Slides
- Dynamically balanced synchronization-avoiding LU factorization with multicore and GPUs Simplice Donfack, Stanimire Tomov and Jack Dongarra Slides
- Scalable Fast Multipole Accelerated Vortex Methods Qi Hu, Nail Gumerov, Rio Yokota, Lorena Barba and Ramani Duraiswamii Slides
Break 3:10 - 3:40 pm
Session 3: Emerging Hybrid Systems (Chair: Michela Taufer, University of Delaware)
3:40 - 4:55 pm
- Infiniband-Verbs on GPU: A case study of controlling an Infiniband network device from the GPU Lena Oden and Holger Fröning Slides
- Programming the Adapteva Epiphany 64-core Network-on-chip Coprocessor Anish Varghese, Robert Edwards, Gaurav Mitra and Alistair Rendell Slides
- High-Performance Zonal Histogramming on Large-Scale Geospatial Rasters Using GPUs and GPU-Accelerated Clusters Jianting Zhang and Dali Wang