The Sixth International Workshop on
Accelerators and Hybrid Exascale Systems
Join us on May 23rd, 2016
Chicago Hyatt Regency, Chicago, IL, USA
To be held in conjunction with
30th IEEE International Parallel and Distributed Processing Symposium

Opening remarks

8:30 - 8:45 am
AsHES General Chair: James Dinan, Intel, USA

[ slides ]

Keynote by Professor Wen-mei W. Hwu

[ slides ]

8:45 - 9:50 am

"Addressing the Accelerator Programming Challenges in Exascale Systems"

Abstract: Since the introduction of CUDA in 2006, we have made tremendous progress in heterogeneous supercomputing. We have built heterogeneous top-ranked supercomputers. Much has been learned about of algorithms, languages, compilers and hardware architecture in this movement. What is the benefit that science teams are seeing? How hard is it to program these systems today? How will we programming these systems in the future? In this talk, I will go over the lessons learned from educating programmers, migrating Blue Waters applications into GPUs, and developing performance-critical libraries. Iwill then give a preview of the types of programming systems that will be needed to further reduce the software cost of heterogeneous computing.

Bio: Wen-mei W. Hwu is the Walter J. ("Jerry") Sanders III-Advanced Micro Devices Endowed Chair in Electrical and Computer Engineering in the Coordinated Science Laboratory of the University of Illinois at Urbana-Champaign. Dr. Hwu received his Ph.D. degree in Computer Science from the University of California, Berkeley, 1987.
His research interests are in the areas of architecture,implementation,software for high-performance computer systems, and parallel processing. He is a Principal Investigator(PI) for the petascale Blue Waters system, is co-director of the Intel and Microsoft funded Universal Parallel Computing Research Center (UPCRC), and PI for the world's first NVIDIA GPU Center of Excellence. At the Illinois Coordinated Science Lab,he is the director of the OpenIMPACT project, which has delivered new compiler and computer architecture technologies to the computer industry since 1987. He also serves as the Soft Systems Theme leader of the MARCO/DARPA Gigascale Silicon Research Center (GSRC) and on the Executive Committees of both the GSRC and the MARCO/DARPA Center for Circuit and System Solutions (C2S2).
For his contributions to the areas of compiler optimization and computer architecture, he received the 1993 Eta Kappa Nu Outstanding Young Electrical Engineer Award, the 1994 Xerox Award for Faculty Research, the 1994 University Scholar Award of the University of Illinois, the 1997 Eta Kappa Nu Holmes MacDonald Outstanding Teaching Award, the 1998 ACM SigArch Maurice Wilkes Award, the 1999 ACM Grace Murray Hopper Award, the 2001 Tau Beta Pi Daniel C. Drucker Eminent Faculty Award, and the 2002 ComputerWorld Honors Archive Medal. He is a fellow of IEEE and of the ACM.
From 1997 to 1999, Prof. Hwu served as chairman of the Computer Engineering Program at the University of Illinois. In 2007 he introduced a new engineering course in massively parallel processing, which he co-taught with David Kirk, Chief Scientist of NVIDIA. In 2008, he was named co-director of one of two Universal Parallel Computing Research Centers sponsored by Microsoft and Intel.

Break 9:50 - 10:20 am

Session 1: Programming Models and Tools

10:20 am - 12:00 pm
Session Chair: Sandra Catalán, Universitat Jaume I, Castellón, Spain

  • Heterogeneous Streaming
    Cj Newburn, Gaurav Bansal, Michael Wood, Luis Crivelli, Judit Planas, Alejandro Duran, Paulo Souza, Leonardo Borges, Piotr Luszczek, Stanimire Tomov, Jack Dongarra, Hartwig Anzt, Mark Gates, Azzam Haidar, Yulu Jia, Khairul Kabir, Ichitaro Yamazaki and Jesus Labarta [ slides ]
  • HMC-Sim-2.0: A Simulation Platform for Exploring Custom Memory Cube Operations
    John Leidel and Yong Chen [ slides ]
  • Alpaka – An Abstraction Library for Parallel Kernel Acceleration
    Erik Zenker, Benjamin Worpitz, René Widera, Axel Huebl, Guido Juckeland, Wolfgang E. Nagel, Michael Bussman and Andreas Knüpfer [ slides ]
  • A Tool for Bottleneck Analysis and Performance Prediction for GPU-accelerated applications
    Souley Madougou, Ana Lucia Varbanescu, Cees De Laat and Rob Van Nieuwpoort [ slides ]

Lunch 12:00 - 1:30 pm

Session 2: Algorithms and Applications

1:30 - 3:10 pm
Session Chair: CJ Newburn, Intel, USA

  • Hessenberg Reduction with Transient Error Resilience on GPU-Based Hybrid Architectures
    Yulu Jia, Piotr Luszczek and Jack Dongarra
  • Optimization of Block Sparse Matrix-Vector Multiplication on Shared-Memory Architectures
    Ryan Eberhardt and Mark Hoemmen [ slides ]
  • Basker: A Threaded Sparse LU Factorization Utilizing Hierarchical Parallelism and Data Layouts
    Joshua Booth, Sivasankaran Rajamanickam and Heidi Thornquist[ slides ]
  • Efficiency of general Krylov methods on GPUs – An experimental study
    Hartwig Anzt, Jack Dongarra, Moritz Kreutzer, Gerhard Wellein and Martin Koehler [ slides-1 ][ slides-2 ]

Break 3:10 - 3:40 pm

Session 3: Workload Scheduling

3:40 - 4:55 pm
Session Chair: Piotr Luszczek, University of Tennessee, Knoxville, USA

  • Refactoring Conventional Task Schedulers to Exploit Asymmetric ARM big.LITTLE Architectures in Dense Linear Algebra
    Luis Costero, Katzalin Olcoz, Francisco D. Igual, Sandra Catalán, Rafael Rodríguez-Sánchez and Enrique S. Quintana-Ortí [ slides ]
  • Heterogeneous CAF-based Load Balancing on Intel Xeon Phi
    Valeria Cardellini, Alessandro Fanfarillo and Salvatore Filippone [ slides ]
  • Topology-Aware GPU Selection on Multi-GPU Nodes
    BEST PAPER AWARD WINNER Iman Faraji, Seyed Hessam Mirsadeghi and Ahmad Afsahi [ slides ]

Closing Remarks

4:55 - 5:00 pm

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