The Seventh International Workshop on
Accelerators and Hybrid Exascale Systems
Join us on May 29th, 2017
Buena Vista Palace Hotel, Orlando, Florida, USA
To be held in conjunction with
31st IEEE International Parallel and Distributed Processing Symposium

Opening remarks

8:45 - 9:00 am
AsHES Program Co-Chair: Antonio J. Peña, Barcelona Supercomputing Center, Spain

Keynote by Tim Mattson

9:00 - 10:00 am

"Accelerators and Exascale Systems: A programmer’s perspective"

Abstract: Life as an HPC researcher used to be so easy. MPI between nodes and OpenMP on a node and you were done. GPUs came along and complicated things, but OpenCL and later the OpenMP device constructs gave us a portable way to write software for nodes composed of CPUs and GPUs. It was awkward but at least you could still build a base of software around portable, open standards.
Now with FPGAs and fixed function accelerators added to the mix, the ability to maintain an application from a single code base has become prohibitively difficult. On top of this, there is no consensus on how we will scale between nodes on an exascale system. Sure, there is always MPI but it’s not clear how the reliability needs of an exascale system will be addressed by MPI. Many new programming models have been suggested, but none of them have proven themselves to be “ready for prime time”. Things are quite confusing.
In this talk we will explore these issues from a programmer’s perspective. We will present a path forward and a workable solution, but in all honesty, there are still too many uncertainties to know the safest approach for an application programmer to take. Which ultimately is the real goal of this talk. We need to get the issues out on the table so we can effectively push the people who build our hardware to work with us to create software solutions that support the needs of our exascale-class applications.

Bio: Tim Mattson is an old-fashioned application programmer. Starting in the sciences (Ph.D. Chemistry, UCSC, 1985) he progressed to high performance computing where he worked with programming models (Linda, MPI, OpenMP, OpenCL, MPI+Fenix) and contributed to influential hardware/software co-design efforts (The first teraflop computing in 1997 and ten years later, the first teraflop chip). Tim is the PI for Intel’s Science and Technology center for Big Data. Among the projects at the center, he has been directly involved with an innovative array storage engine (TileDB), Linear algebra primitives for Graph algorithms (GraphBLAS), and Polystore Database management systems (BigDAWG).

Break 10:00 - 10:30 am

Session 1: Programming Models and Runtime Systems

10:30 am - 12:00 pm
Session Chair: CJ Newburn, NVIDIA, USA

  • Implementing the OpenACC Data Model
    Michael Wolfe, Seyong Lee, Jungwon Kim, Xiaonan Tian, Rengan Xu, Sunita Chandrasekaran and Barbara Chapman
  • Exploring Translation of OpenMP to OpenACC 2.5: Lessons Learned
    Sergio Pino, Lori Pollock and Sunita Chandrasekaran
  • Exploring the Performance Benefit of Hybrid Memory System on HPC Environments
    Ivy Bo Peng, Roberto Gioiosa, Stefano Markidis, Gokcen Kestor, Pietro Cicotti and Erwin Laure

Lunch 12:00 - 1:30 pm

Session 2: Algorithms

1:30 - 3:00 pm
Session Chair: Piotr Luszczek, The University of Tennessee, USA

  • Performance-Portable Sparse Matrix-Matrix Multiplication for Many-Core Architectures
    Mehmet Deveci, Christian Trott and Siva Rajamanickam
  • Time and Energy to Solution Evaluation for the Three-Point Angular Correlation Function
    Antonio Gómez-Iglesias and Miguel Cárdenas-Montes
  • Auto-Tuning Strategies for Parallelizing Sparse Matrix-Vector (SpMV) Multiplication on Multi- and Many-Core Processors
    Kaixi Hou, Wu-Chun Feng and Shuai Che

Break 3:00 - 3:30 pm

Session 3: Scheduling and Architectures

3:30 - 5:00 pm
Session Chair: Antonio Gómez, Texas Advanced Computing Center, USA

  • A Pluggable Framework for Composable HPC Scheduling Libraries
    Max Grossman, Vivek Kumar, Nick Vrvilo, Zoran Budimlic and Vivek Sarkar
  • Static versus Dynamic Task Scheduling of the LU Factorization on ARM big.LITTLE Architectures
    Sandra Catalán, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí and José R. Herrero
  • Benchmarking Sunway SW26010 Manycore Processor
    Zhigeng Xu, James Lin and Satoshi Matsuoka

Closing Remarks

5:00 pm

home : organizers : call for papers : registration : program : submission : contact us